In this work, the junctionless (JL) feature is incorporated in a newly invented device called vertical super-thin body (VSTB) FET and a comparative exploration of DC and analog/RF figures of merit (FoM) is reported for various gate dielectric materials with high-k (Si₃N₄/HfO₂) and low-k (SiO₂) in this novel device through a properly calibrated Sentaurus TCAD tool. A significant minimization of short channel effects by Si₃N₄ and HfO₂ is reflected in all the DC FoM. With respect to SiO₂, off-state leakage current and on-to-off current ratio improves by five (three) orders of magnitude, whereas on current increases by 4.93 (11.83) μA for HfO₂ (Si₃N₄). Further, using HfO₂ (Si₃N₄) as gate dielectric instead of SiO₂, induces a drop of 23.3 (13.91) mV/V in subthreshold swing. The core reason behind such beneficial impact of higher dielectric constant (ε_r) on DC FoM is explained through off-state energy band diagram and bulk electrostatic potential of the device. Besides, though HfO₂/Si₃N₄ increases gate capacitance (C_gg) and gate-drain capacitance (C_gd), both C_gg/C_gd exhibits extremely low values for all the gate dielectrics. Such an attribute helps in achieving higher unit gain cut-off frequency and gain-bandwidth-product. A higher ε_r also influences other analog/RF parameters favorably. It is observed that compared to SiO₂, HfO₂ (Si₃N₄) enhances peak values of transconductance, intrinsic gain, transconductance frequency product, gain frequency product, and gain transconductance frequency product by 37.74 (13.16) μA, 48.08 (24.91), 0.832 (0.278) THz/V, 1.01 (0.465) THz, 34.3 (22.8) THz/V, respectively. This study is intended to establish a broader understanding about the influence of high-k gate dielectrics on the performance of JL VSTB FET.

在这项工作中，无结 (JL) 功能被纳入新发明的称为垂直超薄体 (VSTB) FET 的器件中，并报告了对各种栅极介电材料的 DC 和模拟/RF 品质因数 (FoM) 的比较探索通过正确校准的 Sentaurus TCAD 工具，在这种新型器件中具有高 k (Si ₃ N ₄ /HfO ₂ ) 和低 k (SiO ₂ )。Si ₃ N ₄和HfO ₂对短沟道效应的显着最小化反映在所有DC FoM 中。关于 SiO ₂，断态漏电流和通断电流比提高了五（三）个数量级，而 HfO ₂ (Si ₃ N ₄ ) 的导通电流增加了 4.93 (11.83) μA 。此外，使用 HfO ₂ (Si ₃ N ₄ ) 作为栅极电介质而不是 SiO _{2 会}导致亚阈值摆幅下降 23.3 (13.91) mV/V。较高介电常数 ( ε _r ) 对 DC FoM 的这种有益影响背后的核心原因是通过器件的断态能带图和体静电势来解释的。此外，虽然 HfO ₂ /Si ₃ N ₄增加了栅极电容（C _gg ) 和栅漏电容 ( C _gd )，对于所有栅极电介质，C _gg / C _{gd 都}表现出极低的值。这种属性有助于实现更高的单位增益截止频率和增益带宽积。较高的ε _r也会有利地影响其他模拟/RF 参数。据观察，与 SiO ₂相比，HfO ₂ (Si ₃ N ₄) 将跨导、固有增益、跨导频率乘积、增益频率乘积和增益跨导频率乘积的峰值提高 37.74 (13.16) μA、48.08 (24.91)、0.832 (0.278) THz/V、1.01 (0.465) THz (22.8) THz/V，分别。本研究旨在更广泛地了解高 k 栅极电介质对 JL VSTB FET 性能的影响。