Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.

中文翻译：

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用于下一代物联网网络的低复杂度 LDPC 解码

低密度奇偶校验 (LDPC) 码已成为下一代物联网 (IoT) 网络的焦点选择。这种对应提出了一种有效的解码算法，双最小和 (DMS)，从一组变量节点中估计前两个最小值，用于最小和 (MS) LDPC 解码器的校验节点更新 (CNU) 操作。所提出的架构完全消除了基于排序架构的大型多路复用系统，这导致硬件复杂性和临界延迟的显着降低。具体来说，DMS 架构消除了大量的比较器和多路复用器，同时保持临界延迟等于延迟效率最高的基于树的架构。根据实验结果，如果输入的数量等于 64，则所提出的架构节省了 69%、68%、和基于排序的、基于树的和低复杂度的基于树的体系结构的面积分别为 52%。此外，仿真结果表明，所提出的方法在加性高斯白噪声 (AWGN) 信道上的误码率 (BER) 和误块率 (BLER) 方面提供了出色的纠错性能。