An integrated design based on Gate-All-Around (GAA) silicon Junctionless (JL) vertical profile Nanowire (NW) structure has been proposed for JL-NW-Tunnel-Field Effect Transistor (JL-NW-TFET). A uniform high doping concentration (10⁻¹⁹) has been used to make the device a Junctionless structure. The parametric variations of the JL-NW-TFET have been analyzed such as ON-current (I_ON), OFF-current (I_OFF), ON-OFF ratio of current (I_ON/OFF) and Subthreshold-Slope (SS). Therefore, work function of gate metal (4.4 eV to 4.8 eV), thickness of oxide (1.0 nm to 2.0 nm), diameter of Nanowire (10 nm to 30 nm) and channel length (22 nm to 65 nm) has been varied by implementing device structure in SILVACO Atlas Tools. The optimum parameters of the device have been observed as: maximum I_ON (3.73 × 10⁻⁶ A/μm), minimum I_OFF (2.97 × 10⁻²⁰ A/μm), Low SS (19.40 mV/dec) and high I_ON/OFF (3.35 × 10¹³). It has been proposed that these optimum parameter characteristics are immune to short channel effects and preferred for low power applications in nano regime.

已经为 JL-NW-隧道场效应晶体管 (JL-NW-TFET) 提出了一种基于全环栅 (GAA) 硅无结 (JL) 垂直剖面纳米线 (NW) 结构的集成设计。已使用均匀的高掺杂浓度 (10 ^-19 ) 使器件成为无结结构。已经分析了 JL-NW-TFET 的参数变化，例如导通电流 (I _ON )、截止电流 (I _OFF )、电流的开关比 (I _ON/OFF) 和亚阈值斜率 (SS)。因此，栅极金属的功函数（4.4 eV 到 4.8 eV）、氧化物的厚度（1.0 nm 到 2.0 nm）、纳米线的直径（10 nm 到 30 nm）和沟道长度（22 nm 到 65 nm）已经改变了在 SILVACO Atlas Tools 中实现设备结构。已观察到器件的最佳参数为：最大 I _ON (3.73 × 10 ^-6 A/μm)、最小 I _OFF (2.97 × 10 ^-20 A/μm)、低 SS (19.40 mV/dec) 和高 I_开/关(3.35 × 10 ¹³ )。已经提出，这些最佳参数特性不受短沟道效应的影响，并且更适用于纳米级的低功率应用。