This article presents an analysis of the multiple events [and more specifically, multiple-cell upsets (MCUs)] that may occur at successive generations of bulk CMOS static random access memories (SRAMs) operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS)/International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90- and 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various commercial-off-the-shelf (COTS) SRAMs manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45 down to 14 nm).

中文翻译：

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Bitcell 拓扑对 VLSI 纳米级 SRAM 中观察到的多单元扰乱的影响


本文对在恶劣条件下（例如航空电子设备或太空）运行的连续几代大容量 CMOS 静态随机存取存储器 (SRAM) 可能发生的多个事件 [更具体地说，多单元翻转 (MCU)] 进行了分析。这种MCU分布很大程度上受到bitcell拓扑的影响，在国际半导体技术路线图（ITRS）/国际设备和系统路线图（IRDS）历史中，bitcell拓扑经历了90纳米和65纳米之间过渡的巨大变化节点。提供了从质子和中子加速器获得的实验结果以及 MUSCA-SEP3 建模工具发布的预测。英飞凌在批量 CMOS 130 纳米节点至 65 纳米节点中制造的各种商用现货 (COTS) SRAM 被用作实验结果的目标。最后，MUSCA-SEP3 还用于分析和讨论更现代节点（45 到 14 nm）上的扩展趋势。