The ATLAS Tile Calorimeter (TileCal) readout link and control daughterboard (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity large hadron collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bidirectional fiber-optic links. Two CERN-developed, radiation hard GBTx application specified integrated circuits (ASICs) receive LHC timing signals and configuration commands through 4.8-Gb/s downlinks, which are in turn propagated to the front end through Xilinx Kintex Ultrascale field-programmable gate arrays (FPGAs). The Kintex FPGAs also continuously perform real-time readout and transmission of digitized photomultiplier (PMT) samples, detector control system (DCS) signals, and monitoring data through redundant pairs of 9.6-Gb/s uplinks. The DB design aims at minimizing single points of failure and improving the performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified commercial off-the-shelf (COTS) components. Mitigation of radiation-induced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through forward error correction (FEC) in the downlinks and cyclic redundancy check (CRC) error verification in the redundant uplinks. This article presents the latest revision of the DB (version 6), a redesign that addresses single-event latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the analog-to-digital converter (ADC) read-out, and improved timing performance.

中文翻译：

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适用于 HL-LHC 的 ATLAS Tile 热量计链接子板的修订版


ATLAS Tile 热量计 (TileCal) 读出链路和控制子板 (DB) 是高亮度大型强子对撞机 (HL-LHC) 的新型 TileCal 电子升级的中央探测器集线器。 DB 在开发过程中经历了逐步的重新设计，通过双向光纤链路提供打开和关闭探测器电子设备之间的连接。两个 CERN 开发的抗辐射 GBTx 应用指定集成电路 (ASIC) 通过 4.8 Gb/s 下行链路接收 LHC 定时信号和配置命令，这些信号依次通过 Xilinx Kintex Ultrascale 现场可编程门阵列 (FPGA) 传播到前端）。 Kintex FPGA 还持续执行数字光电倍增器 (PMT) 样本、探测器控制系统 (DCS) 信号的实时读出和传输，并通过冗余的 9.6 Gb/s 上行链路对监控数据。 DB设计旨在最大限度地减少单点故障，提高单板的性能和可靠性。除了 GBTx 器件之外，DB 设计还依赖于符合辐射要求的商用现成 (COTS) 组件。 FPGA 中辐射引起的单粒子翻转 (SEU) 的缓解是通过结合 Xilinx 软错误缓解 (SEM) 控制器和 FPGA 固件中的三模式冗余 (TMR) 方案来实现的。通过下行链路中的前向纠错 (FEC) 和冗余上行链路中的循环冗余校验 (CRC) 错误验证来保护数据完整性。 本文介绍了 DB 的最新版本（版本 6），这是一种重新设计，解决了在先前版本中使用的 Kintex Ultrascale+ FPGA 中观察到的单事件闩锁 (SEL) 行为，并具有更强大的电源电路和改进的电流监控方案、增强的模数转换器 (ADC) 读出性能以及改进的时序性能。