We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and timing analysis to evaluate system-level performance of new CMOS technologies. As the impact of parasitic resistances and capacitances continues to increase with dimensional downscaling, component-level optimization alone becomes insufficient, calling for a holistic assessment and optimization methodology across the boundaries between devices, interconnects, circuits, and systems. The physical implementation flow in DISPEL enables realistic analysis of complex wires and vias in VLSI systems and their impact on the chip power, speed, and area, which simple circuit simulations cannot capture. To demonstrate the use of DISPEL, a 32-bit commercial processor core is implemented using theoretical n-type MoS2 and p-type Black Phosphorous (BP) planar FETs at a projected 5-nm node, and the performance is benchmarked against Si FinFETs. While the superior gate control of the MoS2/BP FETs can theoretically provide 51% reduction in the iso-frequency energy consumption, the actual performance can be greatly limited by the source/drain contact resistances. With the large amount of data generated by DISPEL, a neural-network is trained to predict the key performance metrics of the 32-bit processor core using the characteristics of transistors and interconnects as the input features without the need to go through the time-consuming physical implementation flow. The machine learning algorithms show great potentials as a means for evaluation and optimization of new CMOS technologies and identifying the most significant technology design parameters.

中文翻译：

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设备到系统性能评估：从晶体管/互连建模到 VLSI 物理设计和神经网络预测器

我们提出了一个设备到系统性能评估 (DISPEL) 工作流程，该工作流程集成了晶体管和互连建模、寄生提取、标准单元库表征、逻辑综合、单元布局和布线以及时序分析，以评估新 CMOS 技术的系统级性能. 随着寄生电阻和电容的影响随着尺寸缩小而不断增加，仅靠组件级优化变得不够，需要跨越设备、互连、电路和系统之间的边界的整体评估和优化方法。DISPEL 中的物理实现流程可以对 VLSI 系统中的复杂导线和通孔进行真实分析，以及它们对芯片功率、速度和面积的影响，而这些是简单的电路仿真无法捕捉到的。为了演示 DISPEL 的使用，使用理论上的 n 型 MoS2 和 p 型黑磷 (BP) 平面 FET 在预计的 5 纳米节点上实现了 32 位商业处理器内核，并且性能以 Si FinFET 为基准。虽然 MoS2/BP FET 的卓越栅极控制理论上可以将等频能耗降低 51%，但实际性能可能会受到源/漏接触电阻的极大限制。借助 DISPEL 生成的大量数据，训练神经网络以使用晶体管和互连的特性作为输入特征来预测 32 位处理器内核的关键性能指标，而无需经过耗时的物理实现流程。