Performance optimization is an important goal for High-level Synthesis (HLS). Existing HLS scheduling algorithms are all based on Control and Data Flow Graph (CDFG) and will schedule basic blocks in sequential order. Our study shows that the sequential scheduling order of basic blocks is a big limiting factor for achievable circuit performance. In this article, we propose a Dependency Graph (DG) with two important properties for scheduling. First, DG is a directed acyclic graph. Thus, no loop breaking heuristic is needed for scheduling. Second, DG can be used to identify the exact instruction parallelism. Our experiment shows that DG can lead to 76% instruction parallelism increase over CDFG. Based on DG, we propose a bottom-up scheduling algorithm to achieve much higher instruction parallelism than existing algorithms. Hierarchical state transition graph with guard conditions is proposed for efficient implementation of such high parallelism scheduling. Our experimental results show that our DG-based HLS algorithm can outperform the CDFG-based LegUp and the state-of-the-art industrial tool Vivado HLS by 2.88× and 1.29× on circuit latency, respectively.

中文翻译：

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最大指令并行度的基于依赖图的高级综合

性能优化是高级综合 (HLS) 的一个重要目标。现有的 HLS 调度算法都是基于控制和数据流图 (CDFG) 的，并且会按顺序调度基本块。我们的研究表明，基本块的顺序调度顺序是实现电路性能的一个很大的限制因素。在本文中，我们提出了一个具有两个重要调度属性的依赖图（DG）。首先，DG 是一个有向无环图。因此，调度不需要循环中断启发式。其次，DG 可用于识别确切的指令并行度。我们的实验表明，与 CDFG 相比，DG 可以导致 76% 的指令并行度增加。基于DG，我们提出了一种自底向上的调度算法，以实现比现有算法更高的指令并行度。为了有效实现这种高并行度调度，提出了带有保护条件的分层状态转移图。我们的实验结果表明，我们基于 DG 的 HLS 算法在电路延迟上的性能分别比基于 CDFG 的 LegUp 和最先进的工业工具 Vivado HLS 高 2.88 倍和 1.29 倍。