Modern high-performance server microprocessors need to integrate multiple intellectual property (IP) blocks in a single chip to achieve higher performance. Due to the diverse supply voltage requirements of these IP blocks, their supply voltages are generated locally on the chip using fully integrated voltage regulators (FIVRs). FIVR is designed using on-chip power bridges, bridge drivers, control circuits, on-chip metal–insulator–metal (MIM) capacitors, package inductors, and package power planes. The input power supply (Vccin) of all the FIVRs is shared to minimize the platform cost and is generated using a voltage regulator module (VRM) on the motherboard. The noise coupling between FIVRs due to the common input supply is referred to as the Vccin feedthrough noise. The existing method of modeling the Vccin feedthrough noise is based on circuit simulation. Circuit models are highly complex as different components such as the FIVR power bridges, bridge drivers, MIM capacitors, package inductors, package power planes, and the Vccin network need to be modeled. Convergence issues are very frequent in full chip circuit simulations and it typically takes many iterations. Hence design optimization is difficult to carry out using circuit simulations. In this article, a state-space-based time-domain method is proposed to model the Vccin feedthrough noise based on G-parameters and S-parameters of the FIVR and the Vccin network. The state-space models are generated using the vector-fitting algorithm. The proposed method simplifies the construction of the Vccin feedthrough models and improves the convergence time.

中文翻译：

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基于状态空间的方法对具有完全集成稳压器的微处理器中的 Vccin 馈通噪声进行建模


现代高性能服务器微处理器需要在单个芯片中集成多个知识产权 (IP) 块以实现更高的性能。由于这些 IP 模块的电源电压要求不同，因此它们的电源电压是使用完全集成的电压调节器 (FIVR) 在芯片上本地生成的。 FIVR 的设计采用片上功率桥、桥驱动器、控制电路、片上金属-绝缘体-金属 (MIM) 电容器、封装电感器和封装电源层。所有 FIVR 的输入电源 (Vccin) 都是共享的，以最大限度地降低平台成本，并使用主板上的稳压器模块 (VRM) 生成。由于公共输入电源而导致 FIVR 之间的噪声耦合称为 Vccin 馈通噪声。现有的 Vccin 馈通噪声建模方法基于电路仿真。电路模型非常复杂，因为需要对 FIVR 功率桥、桥驱动器、MIM 电容器、封装电感器、封装电源层和 Vccin 网络等不同组件进行建模。收敛问题在全芯片电路仿真中非常常见，并且通常需要多次迭代。因此，使用电路仿真很难进行设计优化。在本文中，提出了一种基于状态空间的时域方法，根据 FIVR 和 Vccin 网络的 G 参数和 S 参数对 Vccin 馈通噪声进行建模。状态空间模型是使用矢量拟合算法生成的。所提出的方法简化了 Vccin 馈通模型的构造并缩短了收敛时间。