Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature.

中文翻译：

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用于图像处理应用的高速、高能效近似加法器

大多数图像处理应用程序自然是不精确的，并且可以容忍高达特定限制的计算错误。在此类应用中，通过修剪数据路径单元（例如加法器模块）来节省功率。然而，截断可能会导致计算错误，因此，在应用程序中可以容忍的错误量与在面积、功率和延迟方面实现的节省之间始终是一个挑战。本文提出了一种分段近似加法器，以降低容错图像处理应用中的计算复杂度。子进位生成器有助于实现更快的设计，而采用的进位推测方法提高了准确性。综合结果表明，裸片面积减少高达 36.6%，延迟改善高达 62.9%，功耗减少高达 34。与之前发表的类似作品相比，下降了 1%。最后，通过使用图像平滑和锐化技术评估所提出的加法器。对这些应用进行的仿真证明，所提出的加法器获得了比文献中可用的更好的峰值信噪比。