当前位置: X-MOL 学术arXiv.cs.AR › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
arXiv - CS - Hardware Architecture Pub Date : 2021-08-01 , DOI: arxiv-2109.03024
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor Mudge, Chaitali Chakrabarti, David Blaauw, Ronald Dreslinski, Hun-Seok Kim

We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristics in order to optimize bandwidth, access latency, and data reuse. Measured on a set of kernels with diverse data access, control, and synchronization characteristics, reconfiguration between different Versa modes yields median energy-efficiency improvements of 11.6x and 37.2x over mobile CPU and GPU baselines, respectively.

中文翻译:

Versa:以数据流为中心的多处理器,具有 36 个收缩 ARM Cortex-M4F 内核和 28nm 可重配置交叉开关存储器层次结构

我们展示了 Versa,这是一款节能处理器,具有 36 个收缩 ARM Cortex-M4F 内核和运行时可重新配置的存储器层次结构。Versa 利用特定于算法的特性来优化带宽、访问延迟和数据重用。在具有不同数据访问、控制和同步特性的一组内核上进行测量,不同 Versa 模式之间的重新配置分别使移动 CPU 和 GPU 基准的中位能效提高了 11.6 倍和 37.2 倍。
更新日期:2021-09-08
down
wechat
bug