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Augmented Memory Computing: Dynamically Augmented SRAM Storage for Data Intensive Applications
arXiv - CS - Hardware Architecture Pub Date : 2021-07-25 , DOI: arxiv-2109.03022
Haripriya Sheshadri, Shwetha Vijayakumar, Ajey Jacob, Akhilesh Jaiswal

In this paper, we propose a novel memory-centric scheme based on CMOS SRAM for acceleration of data intensive applications. Our proposal aims at dynamically increasing the on-chip memory storage capacity of SRAM arrays on-demand. The proposed scheme called - Augmented Memory Computing allows an SRAM cell to operate in two different modes 1) the Normal mode and 2) the Augmented mode. In the Normal mode of operation, the SRAM cell functions like a standard 6 transistor (6T) SRAM cell, storing one bit of data in static format. While in the Augmented mode, each SRAM cell can store >1 bit of data (in a dynamic fashion). Specifically, we propose two novel SRAM cells - an 8 transistor (8T) dual bit storage augmented cell and a 7 transistor (7T) ternary bit storage augmented cell. The proposed 8T dual bit SRAM cell when operated in the Augmented mode, can store a static bit of data while also, simultaneously, storing another bit in a dynamic form. Thus, when operated in Augmented mode, the 8T SRAM cell can store two bits of data - one SRAM-like data and one DRAM-like data, thereby increasing or augmenting the memory storage capacity. On the other hand, the proposed 7T ternary bit storage augmented cell can either store a single SRAM data in Normal mode or can be configured to operate in Augmented mode, wherein it can store ternary data (3 levels (0,0), (0,1), (1,0)) in a dynamic manner. Thus, based on the mode of operation, the proposed augmented memory bit-cells can either store one static bit of data or >1 bit of data in a dynamic format. We show the feasibility of our proposed bit-cells through extensive simulations at Globalfoundries 22nm FDX node. It is worth mentioning, the novel scheme of augmented memory bit-cells can be seamlessly combined with existing in-memory computing approaches for added energy and throughput benefits.

中文翻译:

增强型内存计算:用于数据密集型应用的动态增强型 SRAM 存储

在本文中,我们提出了一种基于 CMOS SRAM 的新型以内存为中心的方案,用于加速数据密集型应用。我们的提议旨在按需动态增加 SRAM 阵列的片上存储器存储容量。被称为增强存储器计算的提议方案允许 SRAM 单元在两种不同的模式下运行:1) 正常模式和 2) 增强模式。在正常操作模式下,SRAM 单元的功能类似于标准的 6 晶体管 (6T) SRAM 单元,以静态格式存储一位数据。在增强模式下,每个 SRAM 单元可以存储 >1 位数据(以动态方式)。具体来说,我们提出了两种新颖的 SRAM 单元——一个 8 晶体管 (8T) 双位存储增强单元和一个 7 晶体管 (7T) 三元位存储增强单元。建议的 8T 双位 SRAM 单元在增强模式下运行时,可以存储一个静态数据位,同时还可以以动态形式存储另一位数据。因此,当在增强模式下运行时,8T SRAM 单元可以存储两位数据 - 一个类似 SRAM 的数据和一个类似 DRAM 的数据,从而增加或增加内存存储容量。另一方面,建议的 7T 三进制位存储增强单元既可以在正常模式下存储单个 SRAM 数据,也可以配置为在增强模式下运行,其中它可以存储三进制数据(3 个级别 (0,0), (0) ,1), (1,0)) 以动态方式。因此,基于操作模式,所提出的增强存储器位单元可以以动态格式存储一位静态数据或> 1位数据。我们通过 Globalfoundries 22nm FDX 节点的大量模拟展示了我们提出的位单元的可行性。值得一提的是,
更新日期:2021-09-08
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