Two new robust quaternary half adder (QHA) circuits (one single source and one multiple sources) are proposed in this work for low power applications. The proposed circuits are designed in hybrid fashion based on three types of quaternary inverter circuits and compared with recently proposed existing models in terms of number of supplies, power dissipation, delay, power-delay product (PDP) and transistor count through extensive simulations in Cadence Virtuoso platform using Stanford’s Virtual Source-Carbon Nanotube Field Effect Transistor (VS-CNTFET) model. The sensitivity of the circuits in response to process parameters, voltage and temperature (PVT) variations are also evaluated. The proposed circuit with multiple sources has the lowest values of 4.92 uW for power consumption and 0.124 fJ for PDP compared to all other designs. Simulation results also demonstrate better stability to PVT variation for both the proposed architectures with respect to power and PDP parameters. In order to evaluate the competency of the proposed QHAs, quaternary full adder (QFA) circuits are designed using the proposed QHAs and other relevant models. Extensive simulation data confirm that the proposed circuits outperform others in terms of power penalty.

在这项工作中，针对低功率应用提出了两种新的稳健四进制半加器 (QHA) 电路（一个单源和一个多源）。所提出的电路是基于三种类型的四元逆变器电路以混合方式设计的，并通过 Cadence 中的广泛模拟，在电源数量、功耗、延迟、功率延迟积 (PDP) 和晶体管数量方面与最近提出的现有模型进行了比较Virtuoso 平台使用斯坦福的 Virtual Source-Carbon Nanotube Field Effect Transistor (VS-CNTFET) 模型。还评估了电路响应工艺参数、电压和温度 (PVT) 变化的灵敏度。与所有其他设计相比，具有多个源的建议电路的功耗最低为 4.92 uW，PDP 为 0.124 fJ。仿真结果还证明了所提出的架构在功率和 PDP 参数方面对 PVT 变化的更好稳定性。为了评估提议的 QHA 的能力，使用提议的 QHA 和其他相关模型设计了四进制全加器 (QFA) 电路。大量的仿真数据证实，所提出的电路在功率损失方面优于其他电路。