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Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
npj 2D Materials and Applications ( IF 9.1 ) Pub Date : 2021-09-07 , DOI: 10.1038/s41699-021-00257-6
Sadegh Kamaei 1 , Ali Saeidi 1 , Carlotta Gastaldi 1 , Teodor Rosca 1 , Luca Capua 1 , Matteo Cavalieri 1 , Adrian M. Ionescu 1
Affiliation  

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, ION of the order of 100 nA µm−2 and ION/IOFF > 104 at Vd = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.



中文翻译:

从低温到高温的铁电 2D/2D TFET 中的栅极能效和负电容

我们报告了 WSe 2 /SnSe 2隧道 FET (TFET) 中完全集成的铁电栅堆叠的制造工艺和性能特征。在从低温 (77 K) 到 100 °C 的广泛温度范围内,通过实验提取了充电和放电期间栅极堆叠的能量行为,以及开关周期的能量损失和栅极能效因子。获得的结果证实线性极化率在所有研究的温度范围内保持不变,与温度T成反比铁电堆栈。我们表明,低滞后行为是提高能源效率的必要条件,表明人们对真正的 NC 操作制度非常感兴趣。脉冲测量技术显示了在铁电 2D/2D TFET 上实现无滞后负电容 (NC) 效应的可能性。这使得子15毫伏癸-1点亚阈值斜率,20毫伏癸-1平均摆动超过20年的电流,ON 100的顺序的nA的微米-2ON /OFF  > 10 4V d = 1 V。此外,平均摆幅小于 10 mV dec -1在迟滞为 1 V 的 NC TFET 中也获得了超过 1.5 个十倍频程的电流。在无迟滞的 NC-TFET 中实现了高达 50 和 100 V -1的模拟电流效率因子。报告的结果强调,在无滞后状态下,在 NC 中操作铁电栅极堆叠陡坡开关可以实现组合开关能量效率和低能量损失。

更新日期:2021-09-07
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