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Compiler-Driven FPGA Virtualization with SYNERGY
arXiv - CS - Programming Languages Pub Date : 2021-08-28 , DOI: arxiv-2109.02484
Joshua Landgraf, Tiffany Yang, Will Lin, Christopher J. Rossbach, Eric Schkufza

FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3-4x of unvirtualized performance, and incur a modest increase in FPGA fabric utilization.

中文翻译:

使用 SYNERGY 的编译器驱动的 FPGA 虚拟化

FPGA 在现代应用中越来越普遍,云提供商现在支持数据中心的按需 FPGA 加速。数据中心中的应用程序在虚拟基础设施上运行,其中整合、多租户和工作负载迁移可实现规模经济,这是提供商业务的基础。然而,虚拟化 FPGA 的通用策略尚未出现。虽然制造商在基于硬件的方法上苦苦挣扎,但我们提出了一种名为 Synergy 的基于编译器/运行时的解决方案。我们展示了 Verilog 程序的编译器转换,该转换生成的代码能够根据原始程序的语义以亚时钟滴答的粒度将控制权交给软件。Synergy 使用此属性有效地支持核心虚拟化原语:挂起和恢复、程序迁移、和空间/时间复用,在今天可用的硬件上。我们使用 Synergy 在 Amazon F1 上的 Altera SoC 和 Xilinx FPGA 集群中虚拟化 FPGA 工作负载。工作负载无需修改,以非虚拟化性能的 3-4 倍运行,并适度提高 FPGA 架构利用率。
更新日期:2021-09-07
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