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Effect of Wiring Density and Pillar Structure on Chip Packaging Interaction for Mixed-Signal Cu Low k Chips
IEEE Transactions on Device and Materials Reliability ( IF 2.5 ) Pub Date : 2021-05-19 , DOI: 10.1109/tdmr.2021.3082043
Weishen Chu , Tengfei Jiang , Paul S. Ho

Multilevel finite element analysis (FEA) was used to study the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips. The mixed signal chip has analog and digital wiring designs with different metal densities, incorporating extreme low-k (ELK), low-k (LK) and oxide dielectrics in 10 wiring layers. The results are compared with uniform signal chips with uniform metal density on each wiring layer. The first principal stress was found to increase by 1.5 to 3x in the mixed signal chip between the analog and the isolation channel of the ELK and LK layers due to the different wiring density. In addition, the energy release rate (ERR) was significantly increased to reach a critical ERR ratio higher than 1 to drive interfacial delamination, raising serious chip-package interaction (CPI) reliability concern for the mixed signal chip. The results were attributed to the Dundurs effect due to the material mismatch and the nonuniform metal density in the mixed signal chip. In the study of the pillar structure effect, intermetallic compound (IMC) growth was found to be important and can substantially increase the critical ERR ratio to degrade the CPI reliability of the mixed signal chip.

中文翻译:


布线密度和支柱结构对混合信号铜低 k 芯片封装相互作用的影响



采用多级有限元分析 (FEA) 研究布线密度和焊柱结构对先进铜/低 k 混合信号芯片的芯片封装相互作用 (CPI) 的影响。该混合信号芯片具有不同金属密度的模拟和数字布线设计,在 10 个布线层中融入了极低 k (ELK)、低 k (LK) 和氧化物电介质。将结果与各布线层上具有均匀金属密度的均匀信号芯片进行比较。发现由于布线密度不同,ELK 和 LK 层的模拟通道和隔离通道之间的混合信号芯片中的第一主应力增加了 1.5 至 3 倍。此外,能量释放率 (ERR) 显着增加,达到高于 1 的临界 ERR 比,从而导致界面分层,从而引发了混合信号芯片严重的芯片封装相互作用 (CPI) 可靠性问题。该结果归因于混合信号芯片中材料不匹配和金属密度不均匀导致的邓德斯效应。在柱结构效应的研究中,发现金属间化合物(IMC)生长很重要,并且可以大幅增加临界ERR比,从而降低混合信号芯片的CPI可靠性。
更新日期:2021-05-19
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