This work investigates the impact of gate-oxide stacking on the performance of source-pocket engineered (SPE) GaSb/Si heterojunction (HJ) vertical TFETs (VTFETs) based 8T SRAMs. The 8T SRAMs circuits are designed using the SPE-HJ-VTFETs with three different gate-oxide engineered structures: laterally stacked HfO2/Al2O3 gate-oxide, vertically stacked Al2O3/HfO2 gate-oxide and only Al2O3 as gate-oxide. The surface potential, electric field, transfer characteristics, drain characteristics and intrinsic capacitances of all three types of VTFETs considered in this paper are compared. The read static noise margin (RSNM), write margin (WM), read delay as well as write delay of the SRAMs designed by three forms of the SPE GaSb/Si HJ-VTFETs structures have been compared. It is shown that the intrinsic capacitances originated from different stacking-based gate-oxide structures affect the performance of the SRAM significantly. The read delay is significantly the highest for the 8T SRAM designed by laterally stacked gate-oxide based SPE-HJ-VTFETs than the other two 8T SRAMs under consideration. Electrical performance analysis of the VTFETs under study has been studied using commercially available SILVACO ATLAS TCAD tool whereas performance analysis of the 8T SRAMs have been carried out utilizing CADENCE Virtuoso tool by virtue of Verilog A code.

中文翻译：

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横向和垂直栅极氧化物堆叠对采用源袋设计的 GaSb/Si 异质结垂直 TFET 设计的 8T SRAM 的噪声容限和延迟的影响：可靠性研究


这项工作研究了栅极氧化物堆叠对基于源袋工程 (SPE) GaSb/Si 异质结 (HJ) 垂直 TFET (VTFET) 的 8T SRAM 性能的影响。 8T SRAM 电路采用 SPE-HJ-VTFET 设计，具有三种不同的栅极氧化物工程结构：横向堆叠的 HfO2/Al2O3 栅极氧化物、垂直堆叠的 Al2O3/HfO2 栅极氧化物和仅 Al2O3 作为栅极氧化物。本文对所有三种类型 VTFET 的表面电势、电场、传输特性、漏极特性和本征电容进行了比较。比较了三种形式的 SPE GaSb/Si HJ-VTFET 结构设计的 SRAM 的读静态噪声容限 (RSNM)、写容限 (WM)、读延迟和写延迟。结果表明，源自不同堆叠栅极氧化物结构的本征电容显着影响 SRAM 的性能。由横向堆叠栅氧化物基 SPE-HJ-VTFET 设计的 8T SRAM 的读取延迟明显高于其他两个正在考虑的 8T SRAM。使用市售的 SILVACO ATLAS TCAD 工具对所研究的 VTFET 进行电气性能分析，而使用 CADENCE Virtuoso 工具借助 Verilog A 代码对 8T SRAM 进行性能分析。