Pulsed Flip-flops (FFs) are popular elements in the design of high-speed microprocessors. Technology scaling has led to a considerable increase in manufacturing process variation and aging phenomena affecting the reliability of these FFs. In this paper, the timing reliability of pulsed FFs is improved using a transistor-level restructuring technique. In this technique, we modify the pull-down network of pulsed FFs for decreasing the stress time (i.e., the time of being ON) of the pulsed clock transistors. Extensive Monte-Carlo based HSPICE simulations are conducted to show the effectiveness of the proposed restructuring technique under different process variation ratios and lifetime values. The obtained experimental result showed that the lifetime reliability of pulsed FFs is improved by 15% and at the expense of 4% area overhead under 30% process variation ratio and 9 years of operation time.

中文翻译：

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纳米级 CMOS 技术中脉冲触发器的 BTI 感知时序可靠性改进


脉冲触发器 (FF) 是高速微处理器设计中的常用元件。技术扩展导致制造工艺变化和老化现象显着增加，影响了这些 FF 的可靠性。在本文中，使用晶体管级重构技术提高了脉冲 FF 的时序可靠性。在这项技术中，我们修改了脉冲FF的下拉网络，以减少脉冲时钟晶体管的应力时间（即导通时间）。进行了广泛的基于蒙特卡罗的 HSPICE 模拟，以显示所提出的重组技术在不同工艺变化率和寿命值下的有效性。获得的实验结果表明，在30%的工艺变化率和9年的运行时间下，脉冲FF的寿命可靠性提高了15%，并且以4%的面积开销为代价。