In-field test of processor-based devices is a must when considering safety-critical systems (e.g., in robotics, aerospace, and automotive applications). During in-field testing, different solutions can be adopted, depending on the specific constraints of each scenario. In the last years, Self-Test Libraries (STLs) developed by IP or semiconductor companies became widely adopted. Given the strict constraints of in-field test, the size and time duration of a STL is a crucial parameter. This work introduces a novel approach to compress functional test programs belonging to an STL. The proposed approach is based on analyzing (via logic simulation) the interaction between the micro-architectural operation performed by each instruction and its capacity to propagate fault effects on any observable output, reducing the required fault simulations to only one. The proposed compaction strategy was validated by resorting to a RISC-V processor and several test programs stemming from diverse generation strategies. Results showed that the proposed compaction approach can reduce the length of test programs by up to 93.9% and their duration by up to 95%, with minimal effect on fault coverage.

中文翻译：

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SBST 测试程序的新型压缩方法

在考虑安全关键系统（例如，在机器人、航空航天和汽车应用中）时，必须对基于处理器的设备进行现场测试。在现场测试过程中，可以根据每个场景的具体约束采用不同的解决方案。在过去几年中，由 IP 或半导体公司开发的自测库 (STL) 被广泛采用。鉴于现场测试的严格限制，STL 的大小和持续时间是一个关键参数。这项工作引入了一种压缩属于 STL 的功能测试程序的新方法。所提出的方法基于分析（通过逻辑模拟）每条指令执行的微架构操作与其在任何可观察输出上传播故障影响的能力之间的相互作用，将所需的故障模拟减少到只有一个。通过采用 RISC-V 处理器和源自不同生成策略的几个测试程序，对提议的压缩策略进行了验证。结果表明，所提出的压缩方法可以将测试程序的长度减少多达 93.9%，并将其持续时间减少多达 95%，并且对故障覆盖率的影响最小。