ABSTRACT

Rectilinear Steiner tree (RST) construction is an important part of recent VLSI physical design. This article presents an efficient satisfiability (SAT) based approach to construct an obstacle-avoiding Rectilinear Steiner tree for a given set of pins in the presence of a given set of rectilinear obstacles. Initially, a spanning tree is generated without considering the obstacles and the net is decomposed into 2-pin sub-nets. Then, the RST is constructed for each subnet considering obstacles. RST is generated by applying a Pseudo-Boolean (PB) SAT-based technique. The proposed technique has been verified on several benchmark circuits. The results indicate that the proposed technique is able to produce a shorter wire length than other state-of-the-art RST tools in many cases.

摘要

直线施泰纳树（RST）构造是最近VLSI物理设计的重要组成部分。本文提出了一种基于有效可满足性 (SAT) 的方法，用于在存在给定直线障碍物的情况下为给定一组引脚构建避障直线 Steiner 树。最初，在不考虑障碍的情况下生成生成树，并将网络分解为 2 针子网。然后，考虑障碍物，为每个子网构建 RST。RST 是通过应用基于伪布尔 (PB) SAT 的技术生成的。所提出的技术已在多个基准电路上得到验证。结果表明，在许多情况下，所提出的技术能够产生比其他最先进的 RST 工具更短的线长度。