With the continuous scaling of feature sizes, latches are becoming more and more sensitive to the multiple-node upsets (MNUs) induced by radiation. Based on input-split C-elements and a redundant feedback scheme, we propose a triple-node-upset-resilient latch (ISC-TRL) and a quadruple-node-upset-resilient latch (ISC-QRL) to provide high reliability. Using the novel interconnection scheme between the four-level input-split C-elements, any possible triple-node upset (TNU) or quadruple-node upset (QNU) occurred in the proposed latches can be filtered level by level, respectively. HSPICE simulation performed in 14 nm FinFET technology show that, compared with relevant MNU-hardened latches, the proposed ISC-TRL latch can reduce the delay-power-area product (DPAP) by 89.81% and only introduces 3.85% area overhead on average, while achieving 100% TNU-resilience and 99% QNU-resilience. The proposed ISC-QRL latch can reduce the DPAP by 83.01% and introduce 38.46% area overhead on average, while achieving 100% QNU-resilience. In addition, Monte Carlo simulation results show that the proposed ISC-TRL and ISC-QRL latches are of low sensitivity to process, voltage and temperature (PVT) variations.

随着特征尺寸的不断缩放，锁存器对辐射引起的多节点翻转 (MNU) 变得越来越敏感。基于输入拆分 C 元素和冗余反馈方案，我们提出了三节点翻转弹性锁存器 (ISC-TRL) 和四节点翻转弹性锁存器 (ISC-QRL)，以提供高可靠性。使用四级输入拆分 C 元件之间的新型互连方案，可以分别逐级过滤所提出的锁存器中发生的任何可能的三节点翻转 (TNU) 或四节点翻转 (QNU)。在 14 nm FinFET 技术中进行的 HSPICE 仿真表明，与相关的 MNU-hardened 锁存器相比，所提出的 ISC-TRL 锁存器可以将延迟功率面积积 (DPAP) 降低 89.81%，并且平均仅引入 3.85% 的面积开销，同时实现 100% TNU 弹性和 99% QNU 弹性。提出的 ISC-QRL 锁存器可以将 DPAP 降低 83.01%，平均引入 38.46% 的面积开销，同时实现 100% 的 QNU 弹性。此外，蒙特卡罗仿真结果表明，所提出的 ISC-TRL 和 ISC-QRL 锁存器对工艺、电压和温度 (PVT) 变化的敏感性较低。