This paper describes a graph-theoretic formalism and a flow that, to a great extent, automate the design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by Clock Tree Synthesis (CTS) software. In spite of critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. We exploited these similarities and built a design flow and tool set, which uses commercial digital CTS software as an intermediate step. We will explain our flow using a 0.18 micron 10-bit 60 MHz 2-stage pipelined differential-input flash analog-to-digital converter as a test circuit.

中文翻译：

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ACTreS：模拟时钟树合成

本文描述了一种图论形式主义和一个流程，该流程在很大程度上使采样数据模拟电路 (SDAC) 中的时钟树设计自动化。目前 SDAC 时钟树设计的做法是手动过程，既耗时又容易出错。然而，数字域中的时钟树设计是完全自动化的，由时钟树合成 (CTS) 软件执行。尽管存在重大差异，但 SDAC 时钟树设计问题与其数字对应问题具有根本的相似性。我们利用这些相似之处并构建了一个设计流程和工具集，其中使用商业数字 CTS 软件作为中间步骤。我们将使用 0.18 微米 10 位 60 MHz 2 级流水线差分输入闪存模数转换器作为测试电路来解释我们的流程。