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A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware
arXiv - CS - Hardware Architecture Pub Date : 2021-08-27 , DOI: arxiv-2108.12444
Shihao Song, M. Lakshmi Varshika, Anup Das, Nagarajan Kandasamy

The design of many-core neuromorphic hardware is getting more and more complex as these systems are expected to execute large machine learning models. To deal with the design complexity, a predictable design flow is needed to guarantee real-time performance such as latency and throughput without significantly increasing the buffer requirement of computing cores. Synchronous Data Flow Graphs (SDFGs) are used for predictable mapping of streaming applications to multiprocessor systems. We propose an SDFG-based design flow for mapping spiking neural networks (SNNs) to many-core neuromorphic hardware with the objective of exploring the tradeoff between throughput and buffer size. The proposed design flow integrates an iterative partitioning approach, based on Kernighan-Lin graph partitioning heuristic, creating SNN clusters such that each cluster can be mapped to a core of the hardware. The partitioning approach minimizes the inter-cluster spike communication, which improves latency on the shared interconnect of the hardware. Next, the design flow maps clusters to cores using an instance of the Particle Swarm Optimization (PSO), an evolutionary algorithm, exploring the design space of throughput and buffer size. Pareto optimal mappings are retained from the design flow, allowing system designers to select a Pareto mapping that satisfies throughput and buffer size requirements of the design. We evaluated the design flow using five large-scale convolutional neural network (CNN) models. Results demonstrate 63% higher maximum throughput and 10% lower buffer size requirement compared to state-of-the-art dataflow-based mapping solutions.

中文翻译:

将尖峰神经网络映射到多核神经形态硬件的设计流程

众核神经形态硬件的设计越来越复杂,因为这些系统有望执行大型机器学习模型。为了应对设计的复杂性,需要一个可预测的设计流程来保证实时性能,如延迟和吞吐量,而不会显着增加计算内核的缓冲区需求。同步数据流图 (SDFG) 用于将流应用程序可预测地映射到多处理器系统。我们提出了一种基于 SDFG 的设计流程,用于将尖峰神经网络 (SNN) 映射到众核神经形态硬件,目的是探索吞吐量和缓冲区大小之间的权衡。建议的设计流程集成了迭代分区方法,基于 Kernighan-Lin 图分区启发式,创建 SNN 集群,以便每个集群都可以映射到硬件的核心。分区方法最大限度地减少了集群间尖峰通信,从而改善了硬件共享互连的延迟。接下来,设计流程使用粒子群优化 (PSO) 实例(一种进化算法)将集群映射到核心,探索吞吐量和缓冲区大小的设计空间。设计流程中保留了帕累托最优映射,允许系统设计人员选择满足设计吞吐量和缓冲区大小要求的帕累托映射。我们使用五个大型卷积神经网络 (CNN) 模型评估了设计流程。结果表明,与最先进的基于数据流的映射解决方案相比,最大吞吐量提高了 63%,缓冲区大小要求降低了 10%。
更新日期:2021-08-31
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