ABSTRACT

In this paper, clocked differential adiabatic logic families, namely, Clocked CMOS Differential Adiabatic Logic (CCDAL) and Clocked Differential Cascode Adiabatic Logic (CDCAL) pertinent to low power applications have been presented. Charge recovery operation of these circuits are realised by the use of complementary two phase sinusoidal power signals. CCDAL uses clocked control transistor in addition to the differential CMOS logic structure, which makes it suitable for higher-frequency operation. Compared to the existing charge recovery circuits, CCDAL achieves reduced floating nodal output problem resulting in improved drivability and circuit robustness. CDCAL a variant of CCDAL has also been presented which displays enhanced frequency over CCDAL. The feasibility of operating these logic families at a system-level design has been evaluated through design of a digital FIR filter which could be used in magnetic disk drive applications. A four-tap 6-bit FIR filter has been designed using 90 nm CMOS technology library and simulations are carried out using industry standard Cadence® Virtuoso tool. The simulation results prove that proposed adiabatic FIR filter achieves significant energy savings compared to its pipelined static CMOS logic counterpart.

摘要

本文介绍了与低功耗应用相关的时钟差分绝热逻辑系列，即时钟 CMOS 差分绝热逻辑 (CCDAL) 和时钟差分级联绝热逻辑 (CDCAL)。这些电路的电荷恢复操作是通过使用互补的两相正弦功率信号来实现的。CCDAL除了采用差分CMOS逻辑结构外，还采用时钟控制晶体管，使其适用于更高频率的操作。与现有的电荷恢复电路相比，CCDAL 减少了浮动节点输出问题，从而提高了驱动能力和电路鲁棒性。CDCAL CCDAL 的一个变体也被提出，它显示出比 CCDAL 更高的频率。通过设计可用于磁盘驱动器应用的数字 FIR 滤波器，评估了在系统级设计中操作这些逻辑系列的可行性。使用 90 nm CMOS 技术库设计了一个四抽头 6 位 FIR 滤波器，并使用行业标准 Cadence® Virtuoso 工具进行了仿真。仿真结果证明，与流水线静态 CMOS 逻辑对应物相比，所提出的绝热 FIR 滤波器实现了显着的节能效果。