To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

为了满足低轨道航空航天应用对成本效益和高可靠性的要求，本文首先提出了一种抗辐射锁存器设计，即HLCRT。锁存器主要由一个单节点翻转自恢复单元、一个 3 输入 C 元件和一个反相器组成。如果 C 元素的任意两个输入遭受双节点翻转 (DNU)，或者如果单元内的一个节点与单元外的另一个节点一起遭受 DNU，则锁存器在其输出上仍然具有正确的值节点，即锁存器实际上是 DNU 硬化的。基于锁存器，本文还提出了一种触发器，即HLCRT-FF，它可以容忍SNUs和DNUs。仿真结果证明了所提出的 HLCRT 锁存器和 HLCRT-FF 的 SNU/DNU 容错能力。此外，由于使用了少量晶体管、时钟门控技术，