Ternary logic system is the most promising and pursued alternate to the prevailing binary logic systems due to the energy efficiency of circuits following reduced circuit complexity and chip area. In this paper, we have proposed a ternary 3-Transistor Dynamic Random-Access Memory (3T-DRAM) cell using a single word-line for both read and write operation. For simulation of the circuit, we have used Carbon-Nano-Tube Field Effect Transistor (CNTFET). Here, we have analyzed the operation of the circuit considering different process variations and showed the results for write delay, read sensing time, and consumed current. Along with the basic DRAM design, we have proposed a ternary sense circuitry for the proper read operation of the proposed DRAM. The simulation and analysis are executed using the H-SPICE tool with Stanford University CNTFET model.

中文翻译：

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使用 CNTFET 设计具有单字线的新型 3T 三元 DRAM

由于电路复杂度和芯片面积降低后电路的能源效率，三元逻辑系统是最有希望和追求的替代流行的二元逻辑系统的方法。在本文中，我们提出了一种三元 3 晶体管动态随机存取存储器 (3T-DRAM) 单元，它使用单个字线进行读写操作。为了模拟电路，我们使用了碳纳米管场效应晶体管 (CNTFET)。在这里，我们分析了考虑不同工艺变化的电路操作，并展示了写延迟、读感测时间和消耗电流的结果。除了基本的 DRAM 设计外，我们还提出了一种三元检测电路，用于所提议的 DRAM 的正确读取操作。使用 H-SPICE 工具和斯坦福大学 CNTFET 模型执行仿真和分析。