Machine learning is widely used these days to extract meaningful information out of the Zettabytes of sensors data collected daily. All applications require analyzing and understanding the data to identify trends, e.g., surveillance, exhibit some error tolerance. Approximate computing has emerged as an energy-efficient design paradigm aiming to take advantage of the intrinsic error resilience in a wide set of error-tolerant applications. Thus, inexact results could reduce power consumption, delay, area, and execution time. To increase the energy-efficiency of machine learning on FPGA, we consider approximation at the hardware level, e.g., approximate multipliers. However, errors in approximate computing heavily depend on the application, the applied inputs, and user preferences. However, dynamic partial reconfiguration has been introduced, as a key differentiating capability in recent FPGAs, to significantly reduce design area, power consumption, and reconfiguration time by adaptively changing a selective part of the FPGA design without interrupting the remaining system. Thus, integrating “Dynamic Partial Reconfiguration” (DPR) with “Approximate Computing” (AC) will significantly ameliorate the efficiency of FPGA-based design approximation. In this article, we propose hardware-efficient quality-controlled approximate accelerators, which are suitable to be implemented in FPGA-based machine learning algorithms as well as any error-resilient applications. Experimental results using three case studies of image blending, audio blending, and image filtering applications demonstrate that the proposed adaptive approximate accelerator satisfies the required quality with an accuracy of 81.82%, 80.4%, and 89.4%, respectively. On average, the partial bitstream was found to be 28.6 smaller than the full bitstream .

中文翻译：

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基于机器学习和动态部分重配置的有质量保证的近似硬件加速器

如今，机器学习被广泛用于从每天收集的 Zettabytes 传感器数据中提取有意义的信息。所有应用程序都需要分析和理解数据以识别趋势，例如监视，表现出一定的容错性。近似计算已成为一种节能设计范式，旨在利用广泛的容错应用程序中的内在错误恢复能力。因此，不精确的结果可能会降低功耗、延迟、面积和执行时间。为了提高 FPGA 机器学习的能效，我们考虑了硬件级别的近似，例如近似乘法器。然而，近似计算中的错误很大程度上取决于应用程序、应用的输入和用户偏好。但是，引入了动态部分重新配置，作为最新 FPGA 的一项关键差异化能力，通过在不中断其余系统的情况下自适应地更改 FPGA 设计的选择性部分来显着减少设计面积、功耗和重新配置时间。因此，将“动态部分重配置”（DPR）与“近似计算”（AC）集成将显着提高基于 FPGA 的设计逼近的效率。在本文中，我们提出了硬件高效的质量控制近似加速器，适用于基于 FPGA 的机器学习算法以及任何具有容错能力的应用程序中实现。使用图像混合、音频混合和图像过滤应用的三个案例研究的实验结果表明，所提出的自适应近似加速器满足所需的质量，精度为 81。分别为 82%、80.4% 和 89.4%。平均而言，部分比特流被发现是28.6 小于完整的比特流.