In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching ($\frac{I_{ON}}{I_{OFF}}$) behavior with various spacer dielectrics. For optimal values of source ($L_S$) and drain ($L_D$) spacer lengths, the device $\frac{I_{ON}}{I_{OFF}}$ ratio has an improvement of 22.69% and a reduction in $I_{OFF}$ by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with $L_S=L_D=1.5\times L_G$. However, compared to symmetric, the asymmetric spacer exhibits higher $\frac{I_{ON}}{I_{OFF}}$ and lower SS with $L_S=1.5\times L_G$ and $L_D=2.5\times L_G$. Moreover, $L_G$ scaling impact on SS, DIBL, $V_{th}$, and $I_{ON}$ are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and $\frac{I_{ON}}{I_{OFF}}$ ratio of $\sim {10}^8$ even for 5 nm gate length ($L_G$) ensures fundamental scaling. At $L_G$ of 10 nm with asymmetric spacer, a cut-off frequency ($f_T$) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay $\left(\tau \right)$ = 1.3 ps are achieved. Finally, the device exhibits second order harmonic ($g_{m2}$) = 0.2 mA/$V^2$ and third order harmonic ($g_{m3}$) = 1.1 mA/$V^3$ at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.

在本文中，我们首次研究了非对称间隔无结 (JL) 全环栅 (GAA) 垂直堆叠纳米线场效应晶体管 (FET) 的 DC、模拟/RF 和线性度指标增强了亚 5 nm 节点的性能。对对称和非对称间隔长度进行了优化，并将其与亚阈值摆动 (SS) 和开关 ($\frac{{\mathrm{一世}}_{哦N}}{{\mathrm{一世}}_{哦FF}}$) 与各种间隔电介质的行为。对于源的最佳值 (${升}_{秒}$) 和排水 (${升}_D$) 间隔长度，设备 $\frac{{\mathrm{一世}}_{哦N}}{{\mathrm{一世}}_{哦FF}}$ 比率提高了 22.69%，减少了 ${\mathrm{一世}}_{哦FF}$与其他变体相比，高 34.13%。我们的研究表明，在对称垫片变化中，该器件表现出优异的性能${升}_{秒}={升}_D=1.5\times {升}_G$. 然而，与对称相比，非对称间隔表现出更高的$\frac{{\mathrm{一世}}_{哦N}}{{\mathrm{一世}}_{哦FF}}$ 并降低 SS ${升}_{秒}=1.5\times {升}_G$ 和 ${升}_D=2.5\times {升}_G$. 而且，${升}_G$ 扩展对 SS、DIBL、 ${伏}_{吨H}$， 和 ${\mathrm{一世}}_{哦N}$报告了各种间隔。优化的非对称垫片表现出优异的直流特性，SS 为 64 mV/dec 和$\frac{{\mathrm{一世}}_{哦N}}{{\mathrm{一世}}_{哦FF}}$ 比率 $～{10}^8$ 即使对于 5 nm 栅极长度（${升}_G$) 确保基本缩放。在${升}_G$ 10 nm 的非对称间隔，截止频率 ($F_{吨}$) = 0.4 THz，增益带宽积 (GBW) = 0.08 THz，固有延迟 $\left(\tau \right)$= 1.3 ps 达到。最后，该设备表现出二次谐波（$G_{米2}$) = 0.2 毫安/${伏}^2$ 和三次谐波（$G_{米3}$) = 1.1 毫安/${伏}^3$在纳米体制。因此，优化设计的 JL 纳米线 FET 确保了未来技术节点的低功耗、高频率和更好线性度的潜在候选者。