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Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes
Microelectronics Journal ( IF 1.9 ) Pub Date : 2021-08-20 , DOI: 10.1016/j.mejo.2021.105214
V. Bharath Sreenivasulu 1 , Vadthiya Narendar 1
Affiliation  

In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching (IONIOFF) behavior with various spacer dielectrics. For optimal values of source (LS) and drain (LD) spacer lengths, the device IONIOFF ratio has an improvement of 22.69% and a reduction in IOFF by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with LS=LD=1.5×LG. However, compared to symmetric, the asymmetric spacer exhibits higher IONIOFF and lower SS with LS=1.5×LG and LD=2.5×LG. Moreover, LG scaling impact on SS, DIBL, Vth, and ION are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and IONIOFF ratio of 108 even for 5 nm gate length (LG) ensures fundamental scaling. At LG of 10 nm with asymmetric spacer, a cut-off frequency (fT) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay (τ) = 1.3 ps are achieved. Finally, the device exhibits second order harmonic (gm2) = 0.2 mA/V2 and third order harmonic (gm3) = 1.1 mA/V3 at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.



中文翻译:

用于亚 5 nm 技术节点的无结环栅垂直堆叠纳米线 FET 的表征和优化

在本文中,我们首次研究了非对称间隔无结 (JL) 全环栅 (GAA) 垂直堆叠纳米线场效应晶体管 (FET) 的 DC、模拟/RF 和线性度指标增强了亚 5 nm 节点的性能。对对称和非对称间隔长度进行了优化,并将其与亚阈值摆动 (SS) 和开关 (一世N一世FF) 与各种间隔电介质的行为。对于源的最佳值 () 和排水 (D) 间隔长度,设备 一世N一世FF 比率提高了 22.69%,减少了 一世FF与其他变体相比,高 34.13%。我们的研究表明,在对称垫片变化中,该器件表现出优异的性能=D=1.5×G. 然而,与对称相比,非对称间隔表现出更高的一世N一世FF 并降低 SS =1.5×GD=2.5×G. 而且,G 扩展对 SS、DIBL、 H, 和 一世N报告了各种间隔。优化的非对称垫片表现出优异的直流特性,SS 为 64 mV/dec 和一世N一世FF 比率 108 即使对于 5 nm 栅极长度(G) 确保基本缩放。在G 10 nm 的非对称间隔,截止频率 (F) = 0.4 THz,增益带宽积 (GBW) = 0.08 THz,固有延迟 (τ)= 1.3 ps 达到。最后,该设备表现出二次谐波(G2) = 0.2 毫安/2 和三次谐波(G3) = 1.1 毫安/3在纳米体制。因此,优化设计的 JL 纳米线 FET 确保了未来技术节点的低功耗、高频率和更好线性度的潜在候选者。

更新日期:2021-09-03
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