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Pitfalls for transient response analysis with VF-TLP
Microelectronics Reliability ( IF 1.6 ) Pub Date : 2021-08-20 , DOI: 10.1016/j.microrel.2021.114309
Theo Smedes 1 , Mart Coenen 2 , Sander Sluiter 1 , Paul Cappon 1
Affiliation  

Analyzing transient ESD device behavior with TLP equipment requires more attention for implementation and measurement details than the classical quasi-static TLP approach. Minimizing hardware parasitics reduces the de-embedding effort and optimizes the quality of the voltage and current measurements. We explore different methods and hardware options and highlight potential pitfalls.



中文翻译:

使用 VF-TLP 进行瞬态响应分析的陷阱

与经典的准静态 TLP 方法相比,使用 TLP 设备分析瞬态 ESD 器件行为需要更多地关注实施和测量细节。最小化硬件寄生减少了去嵌入工作并优化了电压和电流测量的质量。我们探索了不同的方法和硬件选项,并强调了潜在的陷阱。

更新日期:2021-08-20
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