The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LET _th ) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V.

中文翻译：

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0.2μm DSOI CMOS 技术中重离子引起的单粒子扰动与温度和背栅偏置的相关性


基于 0.2- $\mu \text{m}$ 双绝缘体上硅 (DSOI) 技术研究了温度和背栅偏置对单粒子翻转 (SEU) 灵敏度的依赖性。在室温下，实验观察到 DSOI 静态随机存取存储器 (SRAM) 的 SEU 横截面随着负背栅偏压而明显减小。通过技术计算机辅助设计（TCAD）模拟解释了单粒子效应（SEE）的物理机制。还进行了 TCAD 模拟，以解释不同温度下背栅偏压对电荷收集和脉冲宽度的半峰全宽 (FWHM) 的影响。随着温度从 240 K 升至 400 K，电荷收集和脉冲宽度的 FWHM 均显着增加。结果表明，DSOI 6T SRAM 单元的 SEU 阈值线性能量转移 (LET) 随着温度的升高而降低。与全耗尽型 SOI (FDSOI) 技术相比，DSOI SRAM 单元独特的独立背栅偏置方案对 SEU 具有更高的耐受性。在 400 K 时，发现随着 nMOS 背栅偏压从 0 V 降低至 -15 V，DSOI 6T SRAM 单元的 SEU 阈值 LET (LET _th ) 增加了 12.5%。