In daily increasing integrated circuit complexity, standard cell pin accessibility is becoming more significant part of design process. As pin density is increasing, fast and efficient algorithms for pin-access prediction and optimization are needed. However current methods do not ensure the best trade-off between DRV count decrease and tool runtime optimization.

In this paper pin accessibility checking and optimization method is proposed, which is using machine learning algorithms to increase accuracy of pin-access predictions and decrease DRV count. Results show that with using proposed method, DRV count can be decreased by 47%, while having increase in runtime by 23%.

在日益增加的集成电路复杂性中，标准单元引脚的可访问性正成为设计过程中越来越重要的部分。随着引脚密度的增加，需要快速有效的引脚访问预测和优化算法。然而，当前的方法并不能确保 DRV 计数减少和工具运行时间优化之间的最佳权衡。

在本文中，提出了引脚可访问性检查和优化方法，该方法使用机器学习算法来提高引脚访问预测的准确性并减少 DRV 计数。结果表明，使用所提出的方法，DRV 计数可以减少 47%，同时运行时间增加 23%。