This paper presents a novel CNTFET based design of ternary logics gates where all three ternary logics including standard, positive and negative ternary logic (ST, PT and NT) outputs for each gate are obtained from one structure and are interchangeable through some control inputs. Ternary logic overpowers the conventional binary logic in simplicity and energy efficiency as it reduces number of interconnects and chip area. In this paper design of ternary inverter, buffer, NAND, AND, NOR, OR, XOR and XNOR gates are presented where a unique feature of conversion between ST, PT, NT logic through a single output is being introduced. Besides a single logic gate is designed for a particular logic function and its complement combining both ternary and binary logic gate design technique. The proposed designs utilize the unique property of CNTFET, such as assigning the required threshold voltage value of the FET by changing the diameter of the carbon nanotube (CNT) through its chiral vector values which is very useful in designing multiple- valued logic (here ternary logic). The proposed circuits are simulated using Synopsys HSPICE with 32 nm CNTFET model provided by Stanford University and in each case average power values and propagation delays are duly noted. The effects of variation in some process parameters like channel length, dielectric oxide thickness and number of carbon nanotubes also have been discussed.

本文提出了一种基于 CNTFET 的新型三元逻辑门设计，其中所有三个三元逻辑，包括每个门的标准、正和负三元逻辑（ST、PT 和 NT）输出都是从一个结构获得的，并且可以通过一些控制输入互换。三元逻辑在简单性和能源效率方面优于传统的二元逻辑，因为它减少了互连数量和芯片面积。本文介绍了三元反相器、缓冲器、NAND、AND、NOR、OR、XOR 和 XNOR 门的设计，其中介绍了通过单个输出在 ST、PT、NT 逻辑之间进行转换的独特功能。此外，单个逻辑门是为特定的逻辑功能设计的，其补充结合了三元和二元逻辑门设计技术。所提出的设计利用了 CNTFET 的独特特性，例如，通过改变碳纳米管 (CNT) 的直径及其手性矢量值来分配 FET 所需的阈值电压值，这在设计多值逻辑（此处为三元逻辑）时非常有用。建议的电路是使用 Synopsys HSPICE 和斯坦福大学提供的 32 nm CNTFET 模型进行仿真的，并且在每种情况下都会适当记录平均功率值和传播延迟。还讨论了某些工艺参数（如沟道长度、介电氧化物厚度和碳纳米管数量）变化的影响。建议的电路是使用 Synopsys HSPICE 和斯坦福大学提供的 32 nm CNTFET 模型进行仿真的，并且在每种情况下都会适当记录平均功率值和传播延迟。还讨论了某些工艺参数（如沟道长度、介电氧化物厚度和碳纳米管数量）变化的影响。建议的电路是使用 Synopsys HSPICE 和斯坦福大学提供的 32 nm CNTFET 模型进行仿真的，并且在每种情况下都会适当记录平均功率值和传播延迟。还讨论了某些工艺参数（如沟道长度、介电氧化物厚度和碳纳米管数量）变化的影响。