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A novel SiC power MOSFET with integrated polySi/SiC heterojunction freewheeling diode
Semiconductor Science and Technology ( IF 1.9 ) Pub Date : 2021-07-29 , DOI: 10.1088/1361-6641/ac123c
Shiwei Liang , Hengyu Yu , Hangzhi Liu , Yuwei Wang , Jun Wang

The adoption of intrinsic body diode of SiC MOSFETs as freewheeling diode (FWD) always induces high conduction loss and reverse recovery loss, therefore it is highly desirable to integrate a low loss FWD in SiC MOSFET. In this paper, we propose a new concept of monolithically integrating a polySi/SiC heterojunction diode (HJD) in SiC planar MOSFET (HJDMOS) without sacrificing MOSFET cell density or increasing much processing complexity. The HJD is formed between the gate polysilicon and the SiC JFET region using the same polysilicon deposition, thus the MOSFET and FWD can share the JFET and drift region in a time-multiplexing way. The SiC HJDMOS not only inactivates the body diode by offering lower turn-on voltage but also shows excellent reverse recovery characteristics because the HJD behaves like a Schottky barrier diode. Meanwhile, the gate-to-drain charge (Q gd) and gate-to-drain capacitance (C gd) of the SiC HJDMOS are significantly reduced by 8.0 times and 4.6 times in comparison with the conventional MOSFET due to the reduction of the overlapping area of gate and drain region. With optimal selection of design parameters, the integrated device maintains good MOSFET performances with forward blocking voltage of >1200 V and specific on-resistance (R on,sp) of 2.2 mΩ cm2. Therefore, the obtained figure-of-merits (${R_{{\text{on,sp}}}} \times {Q_{{\text{gd}}}}$ and ${R_{{\text{on,sp}}}} \times {C_{{\text{gd}}}}$) of SiC HJDMOS are improved by around 7.5 times and 4.3 times, respectively. The enhanced performances suggest that SiC HJDMOS is an excellent choice for high efficiency and high frequency power electronic applications.



中文翻译:

一种集成多晶硅/碳化硅异质结续流二极管的新型碳化硅功率MOSFET

采用 SiC MOSFET 的本征体二极管作为续流二极管 (FWD) 总是会引起高传导损耗和反向恢复损耗,因此非常需要在 SiC MOSFET 中集成低损耗 FWD。在本文中,我们提出了一种新概念,即在 SiC 平面 MOSFET (HJDMOS) 中单片集成多晶硅/碳化硅异质结二极管 (HJD),而不会牺牲 MOSFET 单元密度或增加很多加工复杂性。HJD形成在栅极多晶硅和SiC JFET区域之间使用相同的多晶硅沉积,因此MOSFET和FWD可以以时间复用的方式共享JFET和漂移区域。SiC HJDMOS 不仅通过提供较低的导通电压使体二极管失活,而且由于 HJD 的行为类似于肖特基势垒二极管,因此还显示出出色的反向恢复特性。同时, 由于栅漏区重叠面积的减少,SiC HJDMOS的Q gd )和栅漏电容( C gd )比传统MOSFET显着降低了8.0倍和4.6倍。通过优化设计参数选择,集成器件保持良好的 MOSFET 性能,正向阻断电压 >1200 V,比导通电阻 ( R on,sp ) 为 2.2 mΩ cm 2。因此,获得的 SiC HJDMOS 的品质因数(${R_{{\text{on,sp}}}} \times {Q_{{\text{gd}}}}$${R_{{\text{on,sp}}}} \times {C_{{\text{gd}}}}$) 分别提高了约 7.5 倍和 4.3 倍。增强的性能表明 SiC HJDMOS 是高效率和高频电力电子应用的绝佳选择。

更新日期:2021-07-29
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