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High-performance and low-energy approximate full adder design for error-resilient image processing
International Journal of Electronics ( IF 1.1 ) Pub Date : 2021-08-31 , DOI: 10.1080/00207217.2021.1966662
Seyed Hossein Shahrokhi 1 , Mehdi Hosseinzadeh 2 , Midia Reshadi 1 , Saeid Gorgin 3
Affiliation  

ABSTRACT

Full Adder cell is the main building block of larger arithmetic circuits and often is placed along their critical path. Therefore, it is a vital task to design high-performance and low-energy Full Adder cells. In this paper, a novel inexact Full Adder cell is proposed based on carbon nanotube field-effect transistor (CNFET) technology. Comprehensive simulations are carried out at the transistor level by the HSPICE simulator applying the 32 nm Stanford library model. The operation of the proposed cell is investigated with different supply voltages, output loads, ambient temperatures, and operating frequencies. At the application level, the proposed cell is applied to the image blending system by MATLAB software. Simulation results confirm that the proposed cell outperforms its counterparts in terms of both transistor and application-level metrics such as delay, power-delay product (PDP), energy-delay product (EDP), peak signal-to-noise ratio (PSNR), and structural similarity (SSIM) index.



中文翻译:

用于容错图像处理的高性能和低能量近似全加器设计

摘要

全加器单元是大型算术电路的主要构建块,通常沿其关键路径放置。因此,设计高性能、低能耗的全加器单元是一项至关重要的任务。在本文中,提出了一种基于碳纳米管场效应晶体管(CNFET)技术的新型不精确全加器单元。应用 32 nm 斯坦福库模型的 HSPICE 仿真器在晶体管级进行综合仿真。在不同的电源电压、输出负载、环境温度和工作频率下研究了所提出的电池的运行情况。在应用层面,通过MATLAB软件将所提出的单元应用于图像混合系统。

更新日期:2021-08-31
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