This paper presents two efficient ternary SRAM designs appropriate for several transistor-based technologies. The first design is based on the cycle operator in ternary logic while the second is a buffer-based design that employs the positive and negative ternary inverters. Both the designs consume low power in comparison to existing standard ternary inverter-based SRAM designs. Further, the read and write delay for the proposed designs are much lower than the corresponding ones for existing designs. Detailed analyses of the proposed circuits are presented. Extensive HSpice simulations (and comparisons) using a Carbon Nanotube Field Effect Transistor library are reported. The proposed designs also have noise margins comparable to existing designs.

中文翻译：

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应用于 CNTFET 技术的低功耗高性能三态 SRAM 设计


本文介绍了两种适用于多种基于晶体管的技术的高效三态 SRAM 设计。第一个设计基于三元逻辑中的循环运算符，而第二个设计是基于缓冲器的设计，采用正和负三元反相器。与现有的基于标准三态逆变器的 SRAM 设计相比，这两种设计的功耗都很低。此外，所提出的设计的读写延迟远低于现有设计的相应延迟。对所提出的电路进行了详细分析。报告了使用碳纳米管场效应晶体管库进行的广泛 HSpice 模拟（和比较）。所提出的设计还具有与现有设计相当的噪声容限。