The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 V _DD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high I _ON /I _OFF of 10 ¹⁶ , possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of t _FE on noise margin and read-write delay, operated at 0.4 V _DD . The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.

中文翻译：

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作为低于 0.4V VDD 数字逻辑电路的有希望的候选者，异质结负电容隧道 FET

本文的目的是举例说明通过在低于 0.4 V _DD数字逻辑应用中使用负电容隧道 FET 在速度和功耗方面取得的显着改进 。使用 SILVACO TCAD 设计了异质结负电容 TFET (NCTFET)，通过将模拟极化数据与计算出的 LK 方程解正确拟合，证明了其准确性。所提出结构的前景已经体现在 27mV/decade 的陡峭平均亚阈值斜率超过 9 个十年级的电流和10 ^{16 的}高 I _ON /I _OFF ，可能由于内部电压放大和电压钉扎效应。该器件已适用于反相器、环形振荡器、2:1 多路复用器和全加器电路，并使用参考 TFET (R-TFET) 和先前提出的结构在延迟和功耗方面进行了基准测试。还讨论了不同厚度的铁电材料对电路级性能的影响。此外，NCTFET 已在 6-T SRAM 中实现，成功证明了 t _FE对噪声容限和读写延迟的影响，在 0.4 V _{DD 下运行} 。提议的 NCTFET 已被提出并证明是高速和低功耗数字电路的有前途的候选者。