A novel foundry yield model for integrated circuit products has been developed based on critical area scaling. The newly proposed model does not need the information of the defect density by failure mode. This has considerably simplified the model inputs, and avoided the complicated and costly process to obtain the accurate defect density by failure mode. First, the critical area concept and the existing methodology of yield projections are reviewed. Next, a novel product yield model is given based on the critical area scaling. The model tolerance of critical area variations is also discussed. Finally, actual yield data of 14 nm products is compared to the proposed model and the physical area based model. The proposed model has shown significantly improved accuracy to actual silicon data than a physical area based model across a range of products with different design styles and applications. The proposed model is also manufacturing friendly and can be easily adopted by a semiconductor company. The proposed model is not only critical for foundries which have high product mix from different customers, but also beneficial for fabless companies in yield forecast and financial planning.

中文翻译：

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使用临界区域分析的新型铸造产量模型


基于关键面积缩放，开发了一种新颖的集成电路产品代工良率模型。新提出的模型不需要按故障模式划分的缺陷密度信息。这大大简化了模型输入，并避免了通过故障模式获得准确缺陷密度的复杂且昂贵的过程。首先，回顾了关键区域的概念和现有的产量预测方法。接下来，基于临界面积缩放给出了一种新颖的产品良率模型。还讨论了关键区域变化的模型容差。最后，将 14 nm 产品的实际良率数据与所提出的模型和基于物理区域的模型进行比较。在具有不同设计风格和应用的一系列产品中，所提出的模型比基于物理区域的模型显着提高了实际硅数据的准确性。所提出的模型也易于制造，并且可以很容易地被半导体公司采用。所提出的模型不仅对于拥有来自不同客户的高产品组合的代工厂至关重要，而且对于无晶圆厂公司的良率预测和财务规划也有好处。