This work proposes a methodology to find lithography yield detractors using Design Rule Checks (DRC) that are derived from a supervised Machine Learning (ML) model. The probability of being an outlier in layout parameter domain has a strong correlation with the probability of process failure. Moreover, the failing patterns exhibit relatively complex and non-linear behavior and often form complex clusters in the layout parameter domain. Using this, an accurate failure model is built by measuring the distance of a layout sample from the mean distribution in the layout parameter space. The proposed method does not require process failure models, but the calculation of layout parameters only. Further, the failure models are converted into DRC rules to make the methodology suitable for integration into present verification flow. These ML augmented Design Rule Checks (MLDRC) use a set of decision trees in the layout parameter domain and are suitable for full-chip level applications. The ML augmented DRC can better represent and form failure clusters as compared to traditional DRC. Experimental results show that the proposed MLDRC achieves better performance on full-chip designs compared to other hotspot detection techniques.

中文翻译：

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用于识别减产模式的新型 ML 增强型 DRC 框架

这项工作提出了一种方法，可以使用源自监督机器学习 (ML) 模型的设计规则检查 (DRC) 来查找光刻良率减损因素。在布局参数域中成为异常值的概率与工艺失败的概率有很强的相关性。此外，失败的模式表现出相对复杂和非线性的行为，并且经常在布局参数域中形成复杂的集群。使用此方法，通过测量布局样本与布局参数空间中的平均分布的距离来构建准确的故障模型。所提出的方法不需要过程故障模型，而只需要计算布局参数。此外，故障模型被转换为 DRC 规则，使该方法适合集成到当前的验证流程中。这些 ML 增强设计规则检查 (MLDRC) 在布局参数域中使用一组决策树，适用于全芯片级应用。与传统的 DRC 相比，ML 增强的 DRC 可以更好地表示和形成故障集群。实验结果表明，与其他热点检测技术相比，所提出的 MLDRC 在全芯片设计上实现了更好的性能。