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Multiwire Phase Encoding: A Signaling Strategy for High-Bandwidth, Low-Power Data Movement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2021-06-18 , DOI: 10.1109/tvlsi.2021.3087585
Prashansa Mukim , Forrest Brewer

This article presents multiwire phase encoding (MWPE), a transition signaling technique aimed at chip-to-chip communication on silicon interposer technology, where multiple, relatively low-bandwidth transmission lines can be easily routed between high-performance dies. The encoding exploits timing correlation between transitions on multiple band-limited wires to achieve high ensemble bandwidth, potentially exceeding that of parallel conventionally encoded NRZ links. The unambiguous encoding enables instantaneous bit synchronization, resulting in low-power, low-latency, PLL-/DLL-free on-chip data movement. Theoretical and practical bandwidths achievable by phase-encoded links are evaluated as a function of channel properties. Link timing, driver, and receiver circuits are implemented to evaluate the link performance and power costs associated with moving MWPE data. The Hspice simulation-based estimates indicate that a 2-mm-long MWPE link can achieve 126-Gb/s bandwidth on a lossy, dispersive transmission line medium, with an energy cost of 0.24 pJ/bit in 22-nm FDX technology.

中文翻译:


多线相位编码:高带宽、低功耗数据移动的信令策略



本文介绍了多线相位编码 (MWPE),这是一种针对硅中介层技术上的芯片间通信的转换信号技术,其中可以在高性能芯片之间轻松路由多个相对较低带宽的传输线。该编码利用多条带限线路上的转换之间的时序相关性来实现高整体带宽,可能超过并行传统编码 NRZ 链路的带宽。明确的编码可实现瞬时位同步,从而实现低功耗、低延迟、无 PLL/DLL 的片上数据移动。相位编码链路可实现的理论和实际带宽被评估为信道属性的函数。实施链路定时、驱动器和接收器电路来评估与移动 MWPE 数据相关的链路性能和功耗。 Hspice 基于仿真的估计表明,2 毫米长的 MWPE 链路可以在有损、色散传输线介质上实现 126 Gb/s 带宽,而在 22 纳米 FDX 技术中,能源成本为 0.24 pJ/bit。
更新日期:2021-06-18
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