Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell.

中文翻译：

---

基于布局选择性晶体管复制的抗辐射CMOS全加器


由于特征尺寸的不断缩小和工作频率的提高，单粒子瞬态 (SET) 对于现代 CMOS 电路来说已变得越来越成问题。特别是当涉及安全关键或辐射暴露应用时，必须使用硬化技术设计电路。在本简报中，我们展示了一种采用 45 nm 技术的新型抗辐射设计全加器单元。所提出的设计通过基于全面的辐射敏感性分析选择性地复制敏感晶体管来增强瞬态误差。实验结果表明，与未硬化的设计相比，所提出的设计的 SET 灵敏度降低了 62%。此外，相对于应用于未硬化全加器单元的最先进技术，所提出的硬化技术导致性能和功率开销的改进以及零面积开销。