The development of the space–air–ground integration has put higher demands on satellite network. It needs to support high-bandwidth, large-capacity and various quality of service guarantees. However, the satellite onboard switching is facing the problem of resource constraints and special requirements of hardware complexity and scheduling efficiency. For this, this paper proposes a novel memory architecture for high-bandwidth onboard switching fabric. To reduce hardware complexity, multiplexer is used in the input side to merge $k$ input ports into one internal bus, while the output demultiplexer splits an internal bus into $k$ output links. Shared memory architecture is adopted in the input module to improve the memory efficiency, and a buffered crossbar is used to interconnect the input modules to the output modules. A discrete-time queuing model is formulated, and an iterative approach is used to quantitatively analyze the performance of the proposed architecture. The throughput and delay are calculated under different switch size, input load, and buffer capacity. The numerical results can serve as a guidance on deciding the required buffer size and appropriate speedup ratio. This work is validated by both simulations and FPGA implementations. Synthesize result show that using the state-of-the-art Xilinx VU13P FPGA, a switching fabric with 48 ports can be implemented and the peak throughput of the proposed architecture can reach 480 Gbps. Compared with existing combined input-crosspoint queuing, the proposed architecture can significantly reduce the packet delay and the memory resource cost.

天地一体化的发展对卫星网络提出了更高的要求。它需要支持高带宽、大容量和各种服务质量保证。然而，星载交换面临着资源限制以及对硬件复杂度和调度效率的特殊要求的问题。为此，本文提出了一种用于高带宽板载交换结构的新型存储器架构。为了降低硬件复杂度，在输入端使用了多路复用器来合并$克$ 输入端口进入一个内部总线，而输出解复用器将内部总线分成 $克$输出链接。输入模块采用共享内存架构以提高内存效率，并通过缓冲交叉开关将输入模块与输出模块互连。制定了离散时间排队模型，并使用迭代方法对所提出架构的性能进行了定量分析。吞吐量和延迟是在不同的交换机大小、输入负载和缓冲区容量下计算的。数值结果可以作为决定所需缓冲区大小和适当加速比的指导。这项工作得到了仿真和 FPGA 实现的验证。综合结果表明，使用最先进的 Xilinx VU13P FPGA，可以实现具有 48 个端口的交换结构，所提出架构的峰值吞吐量可以达到 480 Gbps。