Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.

中文翻译：

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单通量量子逻辑电路的变化感知保持时间固定方法

单通量量子 (SFQ) 逻辑是一种很有前途的技术，可以替代互补金属氧化物半导体逻辑，用于未来的亿亿级超级计算，但需要开发可靠的 EDA 工具，这些工具适合 SFQ 电路的独特特性，包括对有源分离器以支持扇出和时钟逻辑门。本文是第一篇介绍在 SFQ 电路中插入保持缓冲器的物理设计方法。我们的方法是变化感知的，使用共同路径悲观去除和增量布局，以最大限度地减少时序修复的开销，并且可以权衡布局面积和时序良率。与之前提出的使用固定保持时间裕度的方法相比，蒙特卡罗模拟表明，在 10 个 ISCAS'85 基准电路上进行平均，我们提出的方法可以将插入保持缓冲器的数量减少 8.4%，时序良率提高 6.2%，并且21.9%，时序良率提高 1.7%。