Tools to predict the throughput of basic blocks on a specific microarchitecture are useful to optimize software performance and to build optimizing compilers. In recent work, several such tools have been proposed. However, the accuracy of their predictions has been shown to be relatively low. In this paper, we identify the most important factors for these inaccuracies. To a significant degree these inaccuracies are due to elements and parameters of the pipelines of recent CPUs that are not taken into account by previous tools. A primary reason for this is that the necessary details are often undocumented. In this paper, we build more precise models of relevant components by reverse engineering using microbenchmarks. Based on these models, we develop a simulator for predicting the throughput of basic blocks. In addition to predicting the throughput, our simulator also provides insights into how the code is executed. Our tool supports all Intel Core microarchitecture generations released in the last decade. We evaluate it on an improved version of the BHive benchmark suite. On many recent microarchitectures, its predictions are more accurate than the predictions of state-of-the-art tools by more than an order of magnitude.

中文翻译：

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最新英特尔微架构上基本块的准确吞吐量预测

预测特定微架构上基本块吞吐量的工具对于优化软件性能和构建优化编译器非常有用。在最近的工作中，已经提出了几种这样的工具。然而，他们的预测的准确性已被证明相对较低。在本文中，我们确定了导致这些不准确的最重要因素。在很大程度上，这些不准确是由于以前的工具没有考虑到最新 CPU 的流水线的元素和参数。一个主要原因是必要的细节通常没有记录。在本文中，我们使用微基准通过逆向工程构建了更精确的相关组件模型。基于这些模型，我们开发了一个模拟器来预测基本块的吞吐量。除了预测吞吐量，我们的模拟器还提供了对代码执行方式的洞察。我们的工具支持过去十年发布的所有英特尔酷睿微架构代。我们在 BHive 基准套件的改进版本上对其进行评估。在最近的许多微架构中，它的预测比最先进工具的预测准确度高出一个数量级以上。