Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

中文翻译：

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使用高效率乘法累加单元的低功率转置形式 4 抽头有限脉冲响应滤波器

由于滤波器的稳定性和线性相位响应，有限脉冲响应 (FIR) 滤波器在信号处理应用中得到广泛应用。这些数字滤波器用于生物医学工程、无线通信、图像处理、语音处理、数字音频和视频处理等应用。FIR滤波器的低功耗设计是研究人员努力实现的主要限制之一。本文介绍了一种使用改进的吠陀乘法器 (MVM) 和改进的汉卡尔森加法器 (MHCA) 的 4 抽头 16 位 FIR 滤波器的新型节能设计的实现。这些单元使用 Verilog 硬件描述语言进行编码，并使用 Xilinx Vivado Design Suite 2015.2 进行仿真。该滤波器针对以 xc7a100tcsg324-1 作为目标器件的 7 系列 Artix 现场可编程门阵列进行综合。与现有模型相比，所提出的滤波器设计在功耗方面最大提高了 57.44%，最小提高了 2.44%。