A novel carrier stored trench bipolar transistor (CSTBT) with split gate (SG) and recessed emitter trench (SGRET CSTBT) is proposed. The proposed device features a SG structure with thicker oxide layer under the trench gate and recessed trench emitter, respectively. Compared with the conventional CSTBT with recessed emitter trench (RET CSTBT), the proposed device not only significantly reduces the gate-collector capacitance ( ${C} _{\mathrm{ GC}}$ ) but also alleviates the negative impact of the heavily doped n-type carrier stored layer on the breakdown voltage ( BV ). Simulation results show that with the similar BV of about 650V, the on-state voltage drop ( ${V} _{\mathrm{ ceon}}$ ) at ${J} _{\mathrm{ ce}}$ =200A/cm ² for the proposed SGRET CSTBT is only 1.11V, which is 0.19V lower than that of the conventional RET CSTBT. Moreover, compared with the conventional RET CSTBT, the ${C} _{\mathrm{ GC}}$ at the ${V} _{\mathrm{ ce}}$ of 25V, total gate charge ( ${Q} _{\mathrm{ G}}$ ) and miller plateau charge ( ${Q} _{\mathrm{ GC}}$ ) for the proposed device are reduced by 84.3%, 38.6% and 51.6%, respectively. As a result, the trade-off relationship between the ${V} _{\mathrm{ ceon}}$ and turn-off loss ( ${E} _{\mathrm{ off}}$ ) as well as trade-off relationship between the turn-on loss ( ${E} _{\mathrm{ on}}$ ) and $\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ of the free-wheeling diode (FWD) are significantly improved for the proposed device. At the same ${V} _{\mathrm{ ceon}}$ of 1.16V, the ${E} _{\mathrm{ off}}$ is reduced from 9.2mJ/cm ² of the conventional one to 3.3mJ/cm ² of the proposed device. At the same ${E} _{\mathrm{ on}}$ of 8.3mJ/cm ² , the $\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ of FWD for the proposed device is reduced by 24.5% compared with that of the conventional RET CSTBT, which significantly suppresses the EMI noise.

中文翻译：

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具有分裂栅极和嵌入式发射极沟槽的低损耗和低 EMI 噪声 CSTBT


提出了一种具有分裂栅极（SG）和凹进发射极沟槽（SGRET CSTBT）的新型载流子存储沟槽双极晶体管（CSTBT）。该器件采用 SG 结构，在沟槽栅极和凹进沟槽发射极下方分别具有较厚的氧化层。与传统的带有凹进发射极沟槽的CSTBT（RET CSTBT）相比，所提出的器件不仅显着降低了栅集电极电容（ ${C} _{\mathrm{ GC}}$ ），而且减轻了严重影响的负面影响掺杂n型载流子存储层的击穿电压（BV）。仿真结果表明，在 BV 约为 650V 的情况下，${J} _{\mathrm{ ce}}$ 处的通态压降 ( ${V} _{\mathrm{ ceon}}$ ) =200A/所提出的SGRET CSTBT的cm 2 仅1.11V，比传统的RET CSTBT低0.19V。此外，与传统的RET CSTBT相比，${C} _{\mathrm{ GC}}$在${V} _{\mathrm{ ce}}$为25V时，总栅极电荷( ${Q} _该器件的 {\mathrm{ G}}$ ) 和 miller 平台电荷 ( ${Q} _{\mathrm{ GC}}$ ) 分别减少了 84.3%、38.6% 和 51.6%。因此，${V} _{\mathrm{ ceon}}$ 和关断损耗 ( ${E} _{\mathrm{ off}}$ ) 之间的权衡关系以及权衡开通损耗 ( ${E} _{\mathrm{ on}}$ ) 和 $\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}$ 之间的关系对于所提出的器件，续流二极管 (FWD) 的性能得到显着改进。在${V} _{\mathrm{ ceon}}$为1.16V的情况下，${E} _{\mathrm{ off}}$从传统的9.2mJ/cm 2 减少到3.3mJ/所提议装置的cm 2。在 ${E} _{\mathrm{}}$ 为 8.3mJ/cm 2 时，$\text{d}{V} _{\mathrm{ ak}} / \text{d}{t}拟议设备的 FWD 减少 24 美元。与传统RET CSTBT相比减少5%，显着抑制EMI噪声。