The very large scale integrated (VLSI) circuits become susceptible to soft errors mainly due to exposure to harsh environmental conditions. In this paper, the analysis of total ionizing dose (TID) effects on single gate NMOS, enclosed gate NMOS (ELT NMOS), and single gate PMOS are carried out for 180 nm CMOS technology. The various MOS architectures were exposed to radiation using Cobalt-60 $(C{o}^{60}$) radiation source. The charge density distribution at pre-radiation and post-radiation condition for all the three above said structures are observed. It is observed that the threshold voltage shift for the single gate NMOS device is about 25 times more in comparison to the ELT NMOS device after radiation at 30 Å (Å) gate oxide thickness. The transfer characteristics (drain current versus gate to source voltage) of single gate NMOS is compared for TID from 0 krad to 500 krad with a step size of 100 krad at different oxide thicknesses from 15 Å to 75 Å. It is observed that the drain current increases with an increase in total dose in the sub-threshold region for lower gate oxide thickness (15 Å to 45 Å) while with the increase of gate oxide thickness (beyond 60 Å), the drain current increases significantly for the higher gate to source voltage also. The drain saturation current decreases with the increase of oxide thickness from 15 Å to 75 Å. The impact of TID on single gate PMOS is analysed and no significant effect of radiation observed on threshold voltage or leakage current. The leakage current shift is the least for single gate PMOS among the single gate NMOS, ELT NMOS, and single gate PMOS after radiation of 500 krad total dose. The layouts are designed in Cadence virtuoso software and simulated in Visual TCAD software.

超大规模集成 (VLSI) 电路主要由于暴露于恶劣的环境条件而容易受到软错误的影响。在本文中，针对 180 nm CMOS 技术，对单栅 NMOS、封闭栅 NMOS (ELT NMOS) 和单栅 PMOS 的总电离剂量 (TID) 影响进行了分析。使用 Cobalt-60 将各种 MOS 架构暴露在辐射中$(丙{○}^{60}$) 辐射源。观察了所有上述三种结构在辐射前和辐射后条件下的电荷密度分布。观察到，与 ELT NMOS 器件相比，在 30 埃 (Å) 栅极氧化层厚度下进行辐射后，单栅极 NMOS 器件的阈值电压偏移大约是 ELT NMOS 器件的 25 倍。比较单栅极 NMOS 的传输特性（漏极电流与栅源电压的关系），TID 从 0 krad 到 500 krad，步长为 100 krad，氧化层厚度从 15 Å 到 75 Å。据观察，对于较低的栅氧化层厚度（15 埃到 45 埃），随着栅氧化层厚度的增加（超过 60 埃），漏电流随着亚阈值区域总剂量的增加而增加，对于较高的栅源电压，漏电流也显着增加。漏极饱和电流随着氧化物厚度从 15 Å 增加到 75 Å 而降低。分析了 TID 对单栅极 PMOS 的影响，未观察到辐射对阈值电压或漏电流的显着影响。在单栅NMOS、ELT NMOS和单栅PMOS中，单栅PMOS在500krad总剂量辐射后漏电流漂移最小。布局是在 Cadence virtuoso 软件中设计的，并在 Visual TCAD 软件中进行模拟。在单栅NMOS、ELT NMOS和单栅PMOS中，单栅PMOS在500krad总剂量辐射后漏电流漂移最小。布局是在 Cadence virtuoso 软件中设计的，并在 Visual TCAD 软件中进行模拟。在单栅NMOS、ELT NMOS和单栅PMOS中，单栅PMOS在500krad总剂量辐射后漏电流漂移最小。布局是在 Cadence virtuoso 软件中设计的，并在 Visual TCAD 软件中进行模拟。