A controller PHY for high-capacity DRAM is presented. To reduce precursor and postcursor intersymbol interference due to its dispersive channel characteristics and a heavy load of many DRAM chips and to attenuate reflection on a highly reflective command/address (C/A) channel, a damping-resistor-aided three-tap pulse-based feed-forward equalizer (PB-FFE) is introduced. An appropriate damping resistance can attenuate reflection, and the PB-FFE compensates for increased insertion loss due to the damping resistor. In addition, the current flows only before and after a signal transition in the PB-FFE, improving energy efficiency and maintaining the turn-ON resistance during the no-transition region. A controller PHY based on this equalizer was fabricated in a 55-nm CMOS process. The PB-FFE increases the timing margin of the C/A signal from 0.23 to 0.29 UI at 1067 Mb/s. At 2133 Mb/s, the read timing and voltage margins of the DQ signal are 0.53 UI and 211 mV after read training, and its write margin is 0.72 UI and 230 mV, respectively, after write training.

中文翻译：

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用于具有阻尼电阻辅助脉冲前馈均衡器的托管 DRAM 解决方案的控制器 PHY

提出了一种用于大容量 DRAM 的控制器 PHY。为了减少由于其色散通道特性和许多 DRAM 芯片的重负载而导致的前驱和后驱符号间干扰，并衰减高反射命令/地址 (C/A) 通道上的反射，阻尼电阻器辅助的三抽头脉冲 -引入了基于前馈均衡器（PB-FFE）。适当的阻尼电阻可以衰减反射，而 PB-FFE 可以补偿由于阻尼电阻而增加的插入损耗。此外，电流仅在 PB-FFE 中的信号转换之前和之后流动，从而提高了能量效率并在非转换区域期间保持导通电阻。基于该均衡器的控制器 PHY 采用 55 纳米 CMOS 工艺制造。PB-FFE 将 C/A 信号的时序裕量从 0.23 增加到 0。29 用户界面，1067 Mb/s。在2133 Mb/s时，读训练后DQ信号的读时序和电压余量分别为0.53 UI和211 mV，写训练后其写余量分别为0.72 UI和230 mV。