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Improving Thermal Stability for Ge p-MOSFET of HfO2-Based Gate Stack With Ti-Doped Into Interfacial Layer by In-Situ Plasma-Enhanced Atomic Layer Deposition
IEEE Electron Device Letters ( IF 4.1 ) Pub Date : 2021-06-09 , DOI: 10.1109/led.2021.3087490
Hui-Hsuan Li , Yi-He Tsai , Yu-Hsien Lin , Chao-Hsin Chien

We successfully fabricated a Ge pMOSFET with Ti that is doped into a GeOx interfacial layer (IL) of HfO2 -based gate stacks, doing so using in situ plasma-enhanced atomic layer deposition. X-ray photoelectron spectroscopy (XPS) spectra findings indicated that Ti-doped IL can suppress GeOx volatilization. A Ti-doped GeOx gate stack exhibited a lower interface state density of approximately 6×1011 eV-1 cm-2, an equivalent oxide thickness (EOT) of 0.7 nm, and a relatively low gate leakage current of approximately 10-4 A/cm2 at VFB -1V. Additionally, the Ge pMOSFET with Ti-doped GeOx reveals an improved subthreshold swing of 92 mV/decade and an effective hole mobility of 98 cm2 / V\centerdot s. Therefore, the proposed scheme is simple for use in achieving a sub-nm EOT gate dielectric on a Ge substrate.

中文翻译:


通过原位等离子体增强原子层沉积提高界面层掺钛的 HfO2 基栅极堆叠的 Ge p-MOSFET 的热稳定性



我们使用原位等离子体增强原子层沉积成功地制造了带有 Ti 的 Ge pMOSFET,该 Ti 掺杂到基于 HfO2 的栅极堆叠的 GeOx 界面层 (IL) 中。 X射线光电子能谱(XPS)光谱结果表明,Ti掺杂离子液体可以抑制GeOx的挥发。 Ti掺杂GeOx栅叠层表现出较低的界面态密度,约为6×1011 eV-1 cm-2,等效氧化物厚度(EOT)为0.7 nm,以及相对较低的栅漏电流,约为10-4 A/ cm2,VFB -1V。此外,具有 Ti 掺杂 GeOx 的 Ge pMOSFET 的亚阈值摆幅改善为 92 mV/decade,有效空穴迁移率为 98 cm2 / V\centerdot s。因此,所提出的方案很容易用于在 Ge 衬底上实现亚纳米 EOT 栅极电介质。
更新日期:2021-06-09
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