The low thermal conductivity of Ga ₂ O ₃ has arguably been the most serious concern for Ga ₂ O ₃ power and RF devices. Despite many simulation studies, there is no experimental report on the thermal resistance of a large-area, packaged Ga ₂ O ₃ device. This work fills this gap by demonstrating a 15-A double-side packaged Ga ₂ O ₃ Schottky barrier diode (SBD) and measuring its junction-to-case thermal resistance ( ${R}_{\theta {\mathrm {JC}}}$ ) in the bottom-side- and junction-side-cooling configurations. The ${R}_{\theta \mathrm{JC}}$ characterization is based on the transient dual interface method, i.e., JEDEC 51-14 standard. The ${R}_{\theta \mathrm{JC}}$ of the junction- and bottom-cooled Ga ₂ O ₃ SBD was measured to be 0.5 K/W and 1.43 K/W, respectively, with the former ${R}_{\theta \mathrm{JC}}$ lower than that of similarly-rated commercial SiC SBDs. This low ${R}_{\theta \mathrm{JC}}$ is attributable to the heat extraction directly from the Schottky junction instead of through the Ga ₂ O ₃ chip. The ${R}_{\theta \mathrm{JC}}$ lower than that of commercial SiC devices proves the viability of Ga ₂ O ₃ devices for high-power applications and manifest the significance of proper packaging for their thermal management.

中文翻译：

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采用双面封装的低热阻 (0.5 K/W) Ga₂O₃ 肖特基整流器

Ga ₂ O _{3 的}低热导率 可以说是Ga ₂ O ₃功率和RF器件最严重的问题 。尽管进行了许多模拟研究，但没有关于大面积封装 Ga ₂ O ₃器件热阻的实验报告 。这项工作通过展示 15-A 双面封装 Ga ₂ O ₃肖特基势垒二极管 (SBD) 并测量其结壳热阻来 填补这一空白。 ${R}_{\theta {\mathrm {JC}}}$ ) 在底部侧和结侧冷却配置中。这 ${R}_{\theta \mathrm{JC}}$ 表征基于瞬态双界面方法，即 JEDEC 51-14 标准。这 ${R}_{\theta \mathrm{JC}}$ 结冷却和底部冷却 Ga ₂ O ₃ SBD 的测量值分别为 0.5 K/W 和 1.43 K/W，前者 ${R}_{\theta \mathrm{JC}}$ 低于类似评级的商用 SiC SBD。这个低 ${R}_{\theta \mathrm{JC}}$ 归因于直接从肖特基结而不是通过 Ga ₂ O ₃芯片提取热量 。这 ${R}_{\theta \mathrm{JC}}$ 低于商用 SiC 器件，证明了 Ga ₂ O ₃器件在高功率应用中的可行性， 并表明适当封装对其热管理的重要性。