Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) ZrO2 based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ( tFE and tIL, respectively) on device performance. We observe that a decrease of tFE and tIL reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of tFE, tIL and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood.

中文翻译：

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铁电和界面层厚度对铁电 FET 设计的影响


尽管人们对用于嵌入式、以数据为中心的应用的铁电场效应晶体管 (FEFET) 产生了极大的兴趣，但为了优化性能而在内存窗口 (MW) 和写入电压之间进行基本权衡仍然知之甚少。为此，我们制造了基于铁电 (FE) ZrO2 的 p 型 FEFET，并研究了 FE 和界面氧化层 (IL) 厚度（分别为 tFE 和 tIL）对器件性能的影响。我们观察到，tFE 和 tIL 的降低不仅会降低擦除和编程的写入电压，还会降低存储窗口。这些结果的定量分析为 FEFET 设计提供了以下见解和指导：为了降低写入电压，所有 tFE、tIL 和 FE 的矫顽场都需要降低，并且为了补偿 MW 的后续降低，FE 的极化需要增加 - 尽管仍然需要了解有限元极化程度的可靠性影响。