Purpose

The main purpose of this paper is to propose a quasi-impedance source (QIS) converter fed switched reluctance motor (SRM) drive. The proposed converter topology is configured for DC link capacitance minimization and power factor (PF) correction.

Design/methodology/approach

A QIS converter is used as a front end converter to reduce the bulk capacitance requirement during current commutation and to decline the power ripple. To improve the PF with reduced total harmonic distortion at the input current, the PF current control loop is merged with the QIS converter control loop.

Findings

The overall SRM drive speed is regulated over a wide range by controlling the DC link voltage. The voltage regulation can be achieved by pulse width modulation of the QIS converter. Hence, the overall system efficiency has been improved by operating the proposed converter at a low switching frequency. Moreover, the proposed QIS converter uses an advanced repetitive controller to achieve voltage regulation and fewer ripples in torque.

Originality/value

The steady state and dynamic analyzes have been performed on the proposed drive topology. The performance of the proposed topology has been simulated through MATLAB/Simulink environment. A hardware prototype with a processor of Xilinx SPARTAN 6 field-programmable gate array has been used to validate the experimental response with the simulation results.

中文翻译：

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使用前端转换器提高开关磁阻电机驱动性能

目的

本文的主要目的是提出一种准阻抗源 (QIS) 转换器馈电开关磁阻电机 (SRM) 驱动器。建议的转换器拓扑配置为直流链路电容最小化和功率因数 (PF) 校正。

设计/方法/途径

A QIS converter is used as a front end converter to reduce the bulk capacitance requirement during current commutation and to decline the power ripple. To improve the PF with reduced total harmonic distortion at the input current, the PF current control loop is merged with the QIS converter control loop.

Findings

The overall SRM drive speed is regulated over a wide range by controlling the DC link voltage. The voltage regulation can be achieved by pulse width modulation of the QIS converter. Hence, the overall system efficiency has been improved by operating the proposed converter at a low switching frequency. Moreover, the proposed QIS converter uses an advanced repetitive controller to achieve voltage regulation and fewer ripples in torque.

Originality/value

已对建议的驱动器拓扑结构进行了稳态和动态分析。所提出拓扑的性能已通过 MATLAB/Simulink 环境进行了仿真。具有 Xilinx SPARTAN 6 现场可编程门阵列处理器的硬件原型已用于验证实验响应与仿真结果。